MACH4-96-96-15 Lattice Semiconductor Corp., MACH4-96-96-15 Datasheet - Page 27

• Manufacturer Part Number: MACH4-96-96-15
• Description: High-performance Ee Cmos Programmable Logic
• Manufacturer: Lattice Semiconductor Corp.

f
The parameter f
Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop
designs, f
The first type of design is a state machine with feedback signals sent off-chip. This external feedback
could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest
path defining the period is the sum of the clock-to-output time and the input setup time for the
external signals (t
or in conjunction with an equivalent speed device. This f
The second type of design is a single-chip state machine with internal feedback only. In this case,
flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the
period is limited by the internal delay from the flip-flop outputs through the internal feedback and
logic to the flip-flop inputs. This f
good example of this type of design; therefore, this parameter is sometimes called “f
The third type of design is a simple data path application. In this case, input data is presented to
the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is
limited by the sum of the data setup time and the data hold time (t
for the period of each f
clock period determines the period for the third f
For devices with input registers, one additional f
involves no feedback, it is calculated the same way as f
will be limited either by the sum of the setup and hold times (t
widths (t
specified as 1/(t
path, the overall frequency will be limited by t
calculated from other measured AC parameters. f
MAX
PARAMETERS
f
MAX
WICL
MAX
No Feedback; 1/(t
+ t
is specified for three types of synchronous designs.
LOGIC
LOGIC
f
t
MAX
WICL
t
MAX
S
S
WICH
S
+ t
External 1/(t
is the maximum clock rate at which the device is guaranteed to operate.
+ t
CO
). The clock widths are normally the limiting parameters, so that f
MAX
WICH
). The reciprocal, f
s
+ t
REGISTER
REGISTER
type is the minimum clock period (t
H
). Note that if both input and output registers are used in the same
s
) or 1/(t
+ t
CLK
CLK
CO
t
MAX
CO
)
WH
+ t
is designated “f
WL
MACH4-96/96-15
)
MAX
(SECOND
t
, is the maximum frequency with external feedback
CHIP)
S
ICS
MAX
MAX
. All frequencies except f
MAX
parameter is specified: f
MAX
, designated “f
internal is measured directly.
f
t
MAX
MAXIR
MAX
SIR
internal”. A simple internal counter is a
REGISTER
; 1/(t
no feedback. The minimum period
LOGIC
is designated “f
CLK
SIR
f
WH
t
SIR
MAX
HIR
+ t
+ t
S
Internal (f
+ t
MAX
+ t
HIR
HIR
WL
) or 1/(t
H
). However, a lower limit
) or the sum of the clock
). Usually, this minimum
no feedback.”
REGISTER
CNT
MAX
MAX
LOGIC
WICL
CLK
MAXIR
)
internal are
+ t
external.”
WICH
. Because this
21535A-26
CNT.
)
MAXIR
”
V A N T I S
is
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