MACH4-96-96-15 Lattice Semiconductor Corp., MACH4-96-96-15 Datasheet
MACH4-96-96-15
Related parts for MACH4-96-96-15
MACH4-96-96-15 Summary of contents
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... M4-96/96 nomenclature. Please use the MACH355 data sheet (PID# 17467 reference. GENERAL DESCRIPTION The MACH4-96/96 (M4-96/96 member of Vantis’ high-performance EE CMOS MACH 4 family. This device has approximately three times the macrocell capability of the popular MACH111SP, with significant additional density and functional features. ...
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... Teradyne testers to program MACH devices or test them for connectivity. All MACH devices are supported by industry standard programmers available from a number of vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General. 2 MACH4-96/96-15 ® software ...
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... BLOCK DIAGRAM Clock Generator Clock Generator Clock Generator I2, I5 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE I0/CLK0, I1/CLK1, I3/CLK2, I4/CLK3 MACH4-96/96- Clock Generator OE Clock Generator OE Clock Generator 3 ...
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... Block D TMS = Test Mode Select TCK = Test Clock TDO = Test Data Out TRST = Test Reset ENABLE = Program MACH4-96/96-15 I/O82 I/O81 I/O80 V CC TDO TRST GND I4/CLK3 I3/CLK2 I/O79 I/O78 V CC I/O77 I/O76 GND I/O75 I/O74 I/O73 I/O72 ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confir m availability of specific valid combinations and to check on newly released combinations. MACH4-96/96-15 (Com’ OPERATING CONDITIONS C = Commercial ( +70 C) ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confir m availability of specific valid YI combinations and to check on newly released combinations. MACH4-96/96-18 (Ind) I OPERATING CONDITIONS I= Industrial (– +85 C) PACKAGE TYPE ...
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... Input Switch Matrix Figure 1. MACH4-96/96 Block Diagram and PAL Block Structure The Central Switch Matrix and Input Switch Matrix The M4-96/96 central switch matrix is fed by the input switch matrices in each PAL block. Each PAL block provides 16 internal feedback signals and 16 I/O pin signals to the input switch matrix. ...
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... Figure 2. MACH4-96/96 Input Switch Matrix The Clock Generator Each PAL block has a clock generator that can generate four clock signals for use throughout the PAL block. These four signals are available to all macrocells and I/O cells in the PAL block, whether in synchronous or asynchronous mode ...
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... M10, M11, M12, M13, M14, M15, M8, M9 M11, M12, M13, M14, M15, M8, M9, M10 M12, M13, M14, M15, M8, M9, M10, M11 M13, M14, M15, M8, M9, M10, M11, M12 M14, M15, M8, M9, M10, M11, M12, M13 M15, M8, M9, M10, M11, M12, M13, M14 MACH4-96/96- ...
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... Initialization Product Term From Logic Allocator From PAL-Block Block CLK0 Clock Generator Block CLK1 Individual Clock Product Term 10 SWAP AP AR D/T Synchronous Mode AP AR D/T Asynchronous Mode Figure 4. Macrocell MACH4-96/96-15 To Output and Input Switch Matrices To Output and Input Switch Matrices 21535A-4 ...
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... The direct I/O signal is available to the input switch matrix, and can be used if desired. Macro- cell Macro- cell Macro- cell Macro- cell Macro- cell Macro- cell Macro- cell Macro- cell b. I/O can choose one of 8 macrocells MACH4-96/96 Output Switch Matrix MACH4-96/96- I/O MUX Cell 21535A-5 11 ...
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... JTAG is the commonly used acronym for the IEEE Standard 1149.1-1990. The JTAG standard defines input and output pins, logic control functions, and instructions. Vantis has incorporated this standard into the M4-96/96 device. 12 Individual To Input Switch Matrix Q D/L* Block CLK0 Block CLK1 Block CLK2 Block CLK3 Figure 6. I/O Cell MACH4-96/96-15 21535A-6 ...
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... Input 24 Switch Matrix Figure 7. M4-96/96 PAL Block MACH4-96/96-15 Clock Generator Macrocell I/O Cell I/O Macrocell O1 Cell I/O M2 Macrocell Cell I/O M3 Macrocell Cell I/O M4 Macrocell Cell I/O M5 Macrocell Cell I/O M6 Macrocell Cell I/O M7 Macrocell ...
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... 0 Max OUT CC (Note Outputs Open mA 5.0 V, OUT CC f =25 MHz (Note 5) A and I (or I and I ). OZL IH OZH MACH4-96/96-15 (Com’l) ) Operating A ) with CC Min Typ Max Unit 2.4 0.5 2.0 0.8 10 -100 10 -100 -30 -160 mA 225 mA Characteristics” Chart towards the CC V ...
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... CO Internal Feedback f (CNTA) No Feedback (Note 4) 1/( WLA WHA External 1/( COS Feedback Internal Feedback (f ) CNTS No Feedback (Note4) 1/( WLS WHS MACH4-96/96-15 (Com’ Typ Unit 5 MHz 8 pF -15 Min Max Unit D-type 8 ns T-type ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 16 Parameter Description MACH4-96/96-15 (Com’l) -15 Min Max Unit ...
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... 0 Max OUT CC (Note Outputs Open mA 5.0 V, OUT CC f =25 MHz (Note 5) A (or I and I ). OZL IH OZH MACH4-96/96-18 (Ind with Min Typ Max Unit 2.4 V 0.5 V 2 -100 -100 A -30 -160 mA ...
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... External Feedback 1/( Internal Feedback f (CNTA) No Feedback (Note 4) 1/( WLA WHA External 1/( COS Feedback Internal Feedback (f ) CNTS No Feedback (Note4) 1/( WLS WHS MACH4-96/96-18 (Ind) Typ Unit 5 MHz 8 pF -18 Min Max Unit D-type 10 ns T-type ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. Parameter Description MACH4-96/96-18 (Ind -18 Min ...
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... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH4-96/96-15 V (V) OL 1.0 21535A (V) OH 21535A 21535A-9 ...
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... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH4-96/96- 21535A-10 21 ...
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... Output Combinatorial Output Input, I/ Feedback t H Gate Latched V T Out 21535A-12 MACH4-96/96-15 Typ PQFP Unit 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air 21535A-11 ...
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... V T Input t HIR Input V Register T Clock t ICO Output V T Register Clock 21535A-16 Input Register to Output Register Setup SIL HIL Latched Input MACH4-96/96- GWS 21535A-15 Gate Width ICS V T 21535A- IGO V T 21535A-18 23 ...
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... T 2. Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical IGOL t IGS Latched Input and Output Input V T Latch Gate t WICL 21535A-20 MACH4-96/96-15 t PDLL SLL V T 21535A- WIGL 21535A-21 Input Latch Gate Width ...
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... Input rise and fall times 2 ns–4 ns typical. Input, I/ Feedback Registered V T Output t ARR V T Clock 21535A- – Output Disable/Enable MACH4-96/96- APW APR V T 21535A-23 Asynchronous Preset 21535A-24 25 ...
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... Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State KS000010-PAL Output Test Point Commercial 300 5 pF MACH4-96/96-15 21535A-25 R Measured Output Value 2 1.5 V 390 – ...
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... MAX (SECOND CHIP) LOGIC CLK REGISTER t SIR + 1/( MAXIR MACH4-96/96- external.” MAX ” CNT However, a lower limit Usually, this minimum feedback.” MAX . Because this MAXIR + the sum of the clock SIR ...
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... Clock Width LOW WL Power Registered Output Clock 28 Units 10 Years 20 Years 100 Cycles Power-Up Reset Waveform MACH4-96/96-15 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions can rise CC Max Unit 10 s See Switching Characteristics V CC 21535A-27 ...
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... PIC Designer Concept/Composer Synergy Leapfrog/Verilog-XL Leonardo™ Galileo™ ® SmartModel Design Architect, PLDSynthesis™ II Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator MicroSim Design Lab PLogic, PLSyn PLDesigner-XL™ Software V-System/VHDL OrCAD Express ABEL™ Synario™ Software MACH4-96/96- Library 29 ...
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... Vantis of these products. 30 SOFTWARE DEVELOPMENT SYSTEMS FPGA or Design Compiler (Requires MINC PLDesigner-XL™) VSS Simulator Synplify MultiSIM Interactive Simulator LASAR VeriBest PLD Viewdraw, ViewPLD, Viewsynthesis Speedwave Simulator, ViewSim Simulator, VCS Simulator TEST GENERATION SYSTEM ATGEN™ Test Generation Software PLDCheck 90 MACH4-96/96-15 ...
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... Silver Court Watchmead, Welwyn Garden City Herfordshire UK AL7 1LT 44-1-707-332148 Fax 44-1-707-371503 PROGRAMMER CONFIGURATION Pilot-U40 Pilot-U84 BP1200 BP1400 UniSite™ Model 2900 Model 3900 ALL-07 FLEX-700 Sprint Expert Sprint Optima Stag Quazar MACH4-96/96- MVP BP2100 BP2200 AutoSite Multisite 31 ...
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... Cerritos, California 70703 (310) 926-6727 Vantis Corporation P.O. Box 3755 920 DeGuigne Drive Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com 32 PROGRAMMER CONFIGURATION Turpro-1 Turpro-1/FX PROGRAMMER CONFIGURATION MACH/PAL Programming Adapters Adapt-A-Socket Programming Adapters PROGRAMMER CONFIGURATION JTAGPROG™ MACHPRO MACH4-96/96-15 Turpro-1/TX ® ® ...
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... AMD, Vantis, the Vantis logo and combinations thereof, SpeedLocking and Bus-Friendly are trademarks, MACH, MACHXL, MACHPRO and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 31.00 31.40 27.90 28.10 22.75 REF Pin 72 0.65 BASIC MACH4-96/96- Pin 108 27.90 28.10 31.00 31.40 3.95 MAX SEATING PLANE 16-038-PQR-1_AH ...