MPC8248 Freescale Semiconductor, Inc, MPC8248 Datasheet - Page 57

• Manufacturer Part Number: MPC8248
• Description: Mpc8248 Powerquicc Ii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

11 Document Revision History
Table 22
Freescale Semiconductor
Revision
1.5
1.4
1.3
1.2
1.1
1.0
lists significant changes between revisions of this hardware specification.
12/2006
05/2006
02/2006
09/2005
01/2005
12/2004
Date
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5
•
• Added row for 133 MHz configurations to
• Inserted
• Added 133-MHz to the list of frequencies in the opening sentence of
• Added 133 MHz columns to
• Added footnote 2 to
• Added the conditions note directly above
• Modification for correct display of assertion level (“overbar”) for some signals
• Section 1.1: Added 8:1 ratio to Internal CPM/bus clock multiplier values
• Section 2: removed voltage tracking note
•
•
•
• Section 4.6: Updated description of layout practices
•
•
•
• Section 6: Added sentence providing derating factor
• Section 6.1: added Note: Rise/Fall Time on CPM Input Pins
•
•
• Section 6.2: added spread sprectrum clocking note
• Section 6.2: added CLKIN jitter note
•
•
• Section 7: unit of ns added to Tval notes
• Section 7: Updated all notes to reflect updated CPU Fmin of 150 MHz commercial temp
•
•
•
•
Section 6, “AC Electrical Characteristics,”
timing descriptions.
Characteristics”.
Table
Table
Table
pullup removed.
Table
Table
Table
reflect configurable impedance
Table
sp42, sp43, sp42a
Table
Table
Table
devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Section 7, “Clock Configuration
of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Table
Table
Table
3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset
4: Updated VDD and VCCSYN to 1.425 V - 1.575 V
5: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external
5: Note 3 added regarding IIC compatibility
7: Updated nominal and maximum power dissipation values
8: updated PCI impedance to 27Ω, updated 60x and MEMC values and added note to
9: updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41,
10: updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22
11: combined specs sp11 and sp11a
12: sp30 Data Bus minimum delay values changed to 0.8
20: correct superscript of footnote number after pin AD22
20: remove DONE3 from PC12
20: signals referring to TDMs C2 and D2 removed
Section 6.3, “JTAG Timings.”
Table 22. Document Revision History
Table
12.
Table
Modes”: Updated all table footnotes reflect updated CPU Fmin
Substantive Changes
9,
Table
Table
Table
removed deratings statement and clarified AC
10,
Table
11.
7.
11, and
Table
12.
Section 6, “AC Electrical
Document Revision History
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