TLE84110EL Infineon Technologies, TLE84110EL Datasheet - Page 23

• Manufacturer Part Number: TLE84110EL
• Manufacturer: Infineon Technologies

Specifications of TLE84110EL

• Packages: PG-SSOP-24
• Ipeak: 10 x 0.8
• Inhibit: y
• Iq (typ): 2.0 µA
• Mounting: SMIT
• Technology: BCD

Figure 15
6.2
The SPI is using a standard shift-register concept with daisy-chain capability. Any data transmitted to the SPI will
be available to the internal logic part at the end of the SPI transmission (CSN L -> H). To read a specific register,
the address of the register is sent by the master to the SPI in a first SPI frame. The data that corresponds to this
address is transmitted by the SDO during the following (second) SPI frame to the master. The default address for
Status Register transmission after Power-ON Reset is 0.
The Status-Register-Reset command-bit is executed after the next SPI transmission. The two bits, Address
Register and SRR act as command to read and reset (or not reset) the addressed Status-Register. The request
and response behaviour of the SPI is further illustrated in
Figure 16
Data Sheet
SCLK
CSN
SDO
SDI
SRR 1
SPI SDI, SDO and SCLK
Status Register Reset
Status Register Reset
Request 1
Response 0
SRR 2
23
Request 2
Response 1
Figure 16
below.
SRR 3
Deci Half Bridge IC
Request 3
Response 2
Rev. 1.0, 2010-04-27
TLE84110EL
SPI