SAF7113H/V1,557 NXP Semiconductors, SAF7113H/V1,557 Datasheet - Page 63

• Manufacturer Part Number: SAF7113H/V1,557
• Description: IC VIDEO INPUT PROCESSOR 44-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Processorr

Specifications of SAF7113H/V1,557

• Package / Case: 44-MQFP, 44-PQFP
• Applications: AGP Cards, PCMCIA, Video Phones
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1319; 935263595557; SAF7113HB

Philips Semiconductors
9397 750 14231
Product data sheet
Fig 39. Vertical timing diagram for 60 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR or
input CVBS
RST0/1 HREF
RTS0/1 VREF
RTS0/1 VREF
RTS0/1 VS
RTS0/1 ODD
RTS0/1 V123
RTS0/1 FID
input CVBS
RTS0/1 HREF
RTS0/1 VREF
RTS0/1 VREF
RTS0/1 VS
RTS0/1 ODD
RTS0/1 V123
RTS0/1 FID
(1) Line numbers in parenthesis refer to ITU line counting.
(2) VREF range short or long can be programmed via I
(3) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP (see
(4) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling
HREF: selectable on RTS0 and/or RTS1 via I
ODD: selectable on RTS0 and/or RTS1 via I
VS: selectable on RTS0 and/or RTS1 via I
V123: selectable on RTS0 and/or RTS1 via I
VREF: selectable on RTS0 and/or RTS1 via I
FID: selectable on RTS0 and/or RTS1 via I
bypassed during VREF = 0 if I
NTSC, phase error correcting for PAL) is disabled during VREF = 0.
edge of V123, the field is odd. If HREF is inactive during the falling edge of V123, the field is even. The specific position of
the slope is dependent on the internal processing delay and may change a few clock cycles from version to version.
fast mode (HTC = 01 or 11)]
(3)
(3)
(4)
(4)
VRLN = 1
VRLN = 0
VRLN = 1
VRLN = 0
(262)
259
(525)
522
(2)
(2)
(3) (2)
(3) (2)
(263)
260
523
(1)
(264)
261
524
(2)
2
C-bus bit VBLB is set to logic 1. The chrominance delay line (chrominance-comb filter for
(265)
262
525
(3)
(266)
263
(4)
2
1
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Bh.
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Fh.
2
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Ah.
2
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Ch.
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = Eh.
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7h.
(267)
264
Rev. 03 — 9 May 2005
(5)
2
2
C-bus bit VRLN. The luminance peaking and the chrominance trap are
(268)
265
(6)
3
(a) 1st field
(b) 2nd field
(269)
266
(7)
4
(270)
267
(8)
5
(271)
268
(9)
6
(272)
269
(10)
7
(273)
270
Table
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
(11)
8
9-bit video input processor
81
520
53).
(274)
271
(20)
17
2/LLC
2/LLC
SAF7113H
(283)
280
(21)
18
(284)
281
mhb337
(22)
19
(1)
(285)
282
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(1)