CX24118A-12Z,518 NXP Semiconductors, CX24118A-12Z,518 Datasheet - Page 17

• Manufacturer Part Number: CX24118A-12Z,518
• Description: IC SATELLITE TUNER DGTL 36HVQFN
• Manufacturer: NXP Semiconductors
• Type: Satellite Tunerr

Specifications of CX24118A-12Z,518

• Package / Case: 36-VQFN Exposed Pad, 36-HVQFN, 36-SQFN, 36-DHVQFN
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Bus Type: I2C
• Maximum Agc: 90 dB (Typ)
• Maximum Frequency: 2175 MHz
• Minimum Frequency: 925 MHz
• Mounting Style: SMD/SMT
• Function: Satellite
• Noise Figure: 10 dB
• Operating Supply Voltage: 3.3 V
• Supply Voltage (min): 3.13 V
• Supply Voltage (max): 3.47 V
• Minimum Operating Temperature: 0 C
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287217518

NXP Semiconductors
2.4
CX24118A_N_2
Product data sheet
Local Oscillator and PLL
Table 3.
A bank of six Voltage Controlled Oscillators (VCOs) cover the entire 925 MHz to 2175 MHz
range for downconversion with adequate overlap between VCOs. Each VCO has two bands
of operation, high and low, resulting in a total of 12 virtual VCOs. All the VCOs are integrated
into the chip, eliminating the need for external varactor diodes. The automatic tuning system
selects the appropriate VCO to generate the Local Oscillator (LO), eliminating the need for
calibration during initialization or channel change. The VCOs can also be selected manually,
overriding the automatic tuning system. For more information on the automatic tuning
system, see
The on-chip fractional synthesizer generates the LO with a very fine step size. The fractional
synthesizer consists of a 9-bit integer divider and an 18-bit sigma delta modulator with an 8-
level quantizer. The sigma delta modulator dithers the fractional division ratio to convert
spurious tones and quantization noise to white noise. The charge pump current selection is
based on the VCO tuning voltage, i.e., VCO output frequency. The charge pump tuning
system uses four tuning voltage ranges, and the charge pump current level for each range is
set automatically at every channel change to give optimum integrated phase noise.
The values to be programmed into the PLL’s integer and fractional divider registers are
computed as follows:
RFVCAOff[1:0]
BBVGA2Off[2:0]
BBVGA1Off[2:0]
BBAmpGain[3:0]
FOOTNOTES:
(1)
1.
2.
3.
This value is valid for the CX24116, CX24126, and CX24114 demodulators. For the CX24123
demodulator, use the setting that corresponds to 25 dB.
Set the dividers LODivSel (0x18[6]) and PLLRefDiv (0x02[1]) based on pre-defined or
calculated frequency ranges.
Calculate the total PLL division ratio.
N
=
Calculate the integer divider PLLIntDiv[8:0].
PLLIntDiv[8:0] = Round[N
divider
Parameter
F
--------------------- -
• See
• The Round function rounds the result to the nearest integer.
• PLLIntDiv[8:0] can range from 6d to 511d. This is taken into consideration when
F
VCO
xtal
selecting the divider ranges.
×
=
×
Minimum Signal Level Settings
Section 2.6
2
2
Figure 3
F
--------------------- -
F
; if PLLRefDiv = 1
VCO
xtal
×
×
Rev. 02 — 8 September 2009
2
1
0x20[3:2]
0x1F[5:3]
0x1F[2:0]
0x1D[3:0]
; if PLLRefDiv = 0
for recommended divider settings when using a 40 MHz crystal.
Register Location
divider
] – 32
Register Setting
0011b
011b
010b
10b
Chapter 2: Functional Descriptions
CX24118A
Meaning
31 dB
-64 dB
-29 dB
-32 dB
© NXP B.V. 2009. All rights reserved.
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