CX24118A-12Z,518 NXP Semiconductors, CX24118A-12Z,518 Datasheet
CX24118A-12Z,518
Specifications of CX24118A-12Z,518
Related parts for CX24118A-12Z,518
CX24118A-12Z,518 Summary of contents
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... CX24118A Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 Document information Info Content Keywords Abstract Product data sheet ...
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... CX24118A_N_2 Product data sheet Advanced Modulation Digital Satellite Tuner Description Date Added Figure 12 First NXP version based on the Conexant 102322A data sheet. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 8 September 2009 CX24118A Package 36-pin QFN Description © NXP B.V. 2009. All rights reserved. 2 ...
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... The CX24118A has a built-in auto-tuning system that eliminates the need for software calibration. The on-chip fractional synthesizer enables fine frequency step size without adversely affecting lock time. The CX24118A does not require a balun, thus reducing external BOM cost. Its highly integrated design saves valuable board space and simplifies RF layout ...
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... NXP Semiconductors CX24118A_N_2 Product data sheet Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 4 ...
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... Electrical and Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2.3 Receiver Electrical and Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CX24118A_N_2 Product data sheet Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 5 ...
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... NXP Semiconductors CX24118A_N_2 Product data sheet Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 6 ...
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... Typical Multiple-Bytes Write Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fig. 8 Typical Single-Byte Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Fig. 9 Typical Multiple-Bytes Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Fig. 10 S11 Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Fig. 11 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Fig. 12 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CX24118A_N_2 Product data sheet Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 7 ...
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... NXP Semiconductors CX24118A_N_2 Product data sheet Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 8 ...
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... Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7. Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 8. Thermal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 10. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 11. Receiver Electrical Specifications CX24118A_N_2 Product data sheet Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 9 ...
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... NXP Semiconductors CX24118A_N_2 Product data sheet Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 10 ...
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... Rev. 02 — 8 September 2009 1.1 Pin Diagram Figure 1 Figure 1. Pin Diagram N/C VCC_VCO VTUNE VCC_CP CP_OUT XTAL_BIAS VCC_XTAL XTAL1 XTAL2 CX24118A_N_2 Product data sheet provides a pinout of the CX24118A CX24118A 5 (Exposed Paddle = Gnd Rev. 02 — 8 September 2009 Product data sheet 27 N/C 26 RF_INN ...
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... NXP Semiconductors 1.2 Pin Assignments Table 1 lists the CX24118A pin names, numbers, types, and descriptions. Table 1. Pin Assignments Pin Name Pin Number Type N/C 1 VCC_VCO 2 Power VTUNE 3 Input VCC_CP 4 Power CP_OUT 5 Output XTAL_BIAS 6 Input VCC_XTAL 7 Power XTAL1 8 Input XTAL2 9 Output CKREF_OUT ...
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... This pin has an internal 30 kΩ pull-up resistor. 3.3 V power supply for the prescaler section. The exposed paddle at the bottom of the chip is the common chip ground and the thermal conductor. Rev. 02 — 8 September 2009 CX24118A Chapter 1: Pin Descriptions Description © NXP B.V. 2009. All rights reserved. 13 ...
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... NXP Semiconductors CX24118A_N_2 Product data sheet Rev. 02 — 8 September 2009 CX24118A Chapter 1: Pin Descriptions © NXP B.V. 2009. All rights reserved. 14 ...
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... OUTRefDiv 2.2 Downconverter and Baseband Filtering The L band input from the LNB is fed into the CX24118A either differentially or single-ended. The input signal goes through a low-noise amplification block and is downconverted to a baseband frequency by quadrature downconversion. The output of the downconverter is band limited by a variable bandwidth filter that can be set to 35, 40, 65, or 100 MHz. A ...
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... Gain Settings The CX24118A is controlled by a single AGC signal, providing a dynamic range of 90 dB. The gain stages include an LNA (Low Noise Amplifier) and VCA (Voltage Controlled Attenuator), VGA1 (Variable Gain Amplifier 1), VGA2, and a final amplifier. These gain stages are shown in figure 2-1. ...
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... MHz crystal. × VCO = --------------------- - ; if PLLRefDiv = 0 × xtal × PLLRefDiv = 1 × – 32 divider selecting the divider ranges. Rev. 02 — 8 September 2009 CX24118A Chapter 2: Functional Descriptions Register Setting Meaning 10b -64 dB 011b -29 dB 010b -32 dB (1) 0011b 31 dB © NXP B.V. 2009. All rights reserved. 17 ...
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... PLLFracDiv[17:0] = 0.5, the closest fractional value outside of the keep-out range should be used. f (MHz) 4 below 1165 MHz in order to keep the VCO frequency out of the input frequency range of 925 ÷ Rev. 02 — 8 September 2009 CX24118A Chapter 2: Functional Descriptions - PLLIntDiv[8:0] - 32)] (3) 1500 2175 REN_003 © ...
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... OUTRefDiv = 1 mode is used, the XTAL_BIAS pin needs to be grounded) OUTRefDiv To System : 2 XTAL1 XTAL2 Recommended Component Values for Third-Overtone Crystal Oscillator External Circuit Component Rev. 02 — 8 September 2009 CX24118A Chapter 2: Functional Descriptions Table 4. The external Demodulator Value 390 nH © NXP B.V. 2009. All rights reserved. . 102322_014 19 ...
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... Automatic Tuning System The CX24118A uses an automatic tuning system to select the VCO and band during channel change. The system selects among the 12 virtual VCOs (VCO1–VCO6, each with a high and low band) based on preload values that are programmed during initialization. The automatic tuning system does not require time-consuming calibration during initialization or channel change ...
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... After lock, the charge pump values are automatically selected, based on the VCO tuning voltage and the charge pump initialization values. CX24118A_N_2 Product data sheet Section 2.4 Section for more detail. Rev. 02 — 8 September 2009 CX24118A Chapter 2: Functional Descriptions 2.4, and start the tuning process as © NXP B.V. 2009. All rights reserved. 21 ...
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... NXP Semiconductors CX24118A_N_2 Product data sheet Chapter 2: Functional Descriptions Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 22 ...
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... Every data word is 8 bits long with MSB first, followed by an acknowledge bit generated by the receiving device. Each data transaction occurs between a START and a STOP condition. The START condition is followed by a slave address. If this is the CX24118A address, it generates an acknowledge bit on the SDA line. ...
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... Typical Single-Byte Read Procedure 1. Send the Start condition. 2. Send the CX24118A slave address, a write bit, and receive an ACK. 3. Send the CX24118A desired register address = n, and receive an ACK. 4. Send the Start condition. 5. Send the part's slave address, a read bit, and receive an ACK. 6. ...
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... Slave Master Multiple-Bytes Read Procedure 1. Send the Start condition. 2. Send the CX24118A slave address, a write bit, and receive an ACK. 3. Send the CX24118A desired register address = n, and receive an ACK. 4. Send the Start condition. 5. Send the part's slave address, a read bit, and receive an ACK. ...
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... Table Global CHPId[7:0] CHPVer[7:0] Reserved Tuner DSMByp CPMan[1:0] CPLevel2[1:0] BsDelayVal[3:0] Reserved TUN2[7:0] TUN3[7:0] TUN4[7:0] LODivSel VCOSel[4:0] PLLIntDiv[8:1] PLLFracDiv[17:11] Rev. 02 — 8 September 2009 CX24118A A S Dev Addr/rd Master Data (n+ Slave Master OUTRefDiv PLLRefDiv Reserved CPDVal[1:0] TUNLD CPSel CPLevel3[1:0] CPLevel4[1:0] Reserved CPCtrl CPVal[1:0] ...
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... Chip Version Number. Charge Pump Control. Digital Charge Pump Valve. Charge Pump Enable. Automatic Charge Pump Level 1 Select. Automatic Charge Pump Level 2 Select. Automatic Charge Pump Level 3 Select. Automatic Charge Pump Level 4 Select. Rev. 02 — 8 September 2009 CX24118A Reserved BBFAmpGain[3:0] BBFil2BW[5:0] BBVGA1Off[2:0] ...
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... Tuning System Configuration Register 1. Tuning System Configuration Register 2. Tuning System Configuration Register 3. Tuning System Configuration Register 4. Auto-tuning System Enable. PLL Lock Detect. Tuning System Reset. VCO Band Select. VCO Select. Rev. 02 — 8 September 2009 CX24118A Description © NXP B.V. 2009. All rights reserved. 28 ...
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... Chapter 3: Serial Programming Interface and Registers POR refers to power-on reset value. All bits in the registers are Read/Write unless indicated otherwise in the bit description CHPId[7: CHP Ver[7: Reserved DSMByp CPMan[1:0] Rev. 02 — 8 September 2009 CX24118A OUTRefDiv PLLRefDiv Reserved Section 2.5 for more detail CPDVal[1:0] ...
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... CPSel 0 = Automatic charge pump current selection Manual charge pump current selection. Register 11 Register POR D7 (Hex CPLevel1[1:0] CX24118A_N_2 Product data sheet Chapter 3: Serial Programming Interface and Registers CPLevel2[1:0] Rev. 02 — 8 September 2009 CX24118A CPLevel3[1:0] CPLevel4[1:0] © NXP B.V. 2009. All rights reserved. 30 ...
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... Read only. 00b = 0.5 mA. 01b = 1.0 mA. 10b = 1.5 mA. 11b = 2.0 mA. Register 14 Register POR D7 (Hex TUNAutoEn[1:0] CX24118A_N_2 Product data sheet Chapter 3: Serial Programming Interface and Registers BsDelayVal[3:0] Reserved Rev. 02 — 8 September 2009 CX24118A CPCtrl CPVal[1: TUN1[5:0] © NXP B.V. 2009. All rights reserved. 31 ...
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... Tuning System Configuration Register 4. TUN4[7:0] For normal operation, set to 0xF0. Register 18 Register POR D7 (Hex VCOSel[5] CX24118A_N_2 Product data sheet Chapter 3: Serial Programming Interface and Registers TUN2[7: TUN3[7: TUN4[7: LODivSel VCOSel[4:0] Rev. 02 — 8 September 2009 CX24118A VCOBandSel © NXP B.V. 2009. All rights reserved. 32 ...
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... Use this setting under all conditions. 0111b = 28 dB gain. 1111b = 25 dB gain. CX24118A_N_2 Product data sheet Chapter 3: Serial Programming Interface and Registers PLLIntDiv[8:1] PLLFracDiv[17:11] PLLFracDiv[10:3] TUNReset Reserved Rev. 02 — 8 September 2009 CX24118A Reserved BBFAmpGain[3:0] © NXP B.V. 2009. All rights reserved. 33 ...
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... Use this setting for maximum signal levels. Register 20 Register POR D7 (Hex CX24118A_N_2 Product data sheet Chapter 3: Serial Programming Interface and Registers BBVGA2Off[2: Reserved RFVCABCDis Rev. 02 — 8 September 2009 CX24118A BBFil2BW[5: BBVGA1Off[2: RFVCAOff[1:0] Reserved © NXP B.V. 2009. All rights reserved. 34 ...
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... Enable Disable. DC Offset Correction Enable. DCCorrEn 1 = Enable Disable. RF VCA Enable. RFVCAEn 1 = Enable Disable. CX24118A_N_2 Product data sheet Chapter 3: Serial Programming Interface and Registers CPEn PSEn BBEn Rev. 02 — 8 September 2009 CX24118A DCCorrEn Reserved RFVCAEn © NXP B.V. 2009. All rights reserved. 35 ...
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... NXP Semiconductors CX24118A_N_2 Product data sheet Chapter 3: Serial Programming Interface and Registers Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 36 ...
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... Rev. 02 — 8 September 2009 4.1 Thermal Recommendations The CX24118A uses a thermally enhanced QFN package with an exposed paddle underneath the device to dissipate heat. The exposed paddle is soldered directly to exposed PCB ground on the top layer of the board. Thermal vias then connect the top PCB layer to the other board layers ...
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... NXP Semiconductors CX24118A_N_2 Product data sheet Chapter 4: Application Information Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 38 ...
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... Impedance = Z0 * (0.304 - j0.547 Frequency = 925.0 MHz S (1,1) = 0.482 / -84.258 Impedance = Z0 * (0.676 - j0.845), where Ω 3. The measurement was taken at the input of the device using a short 50 Ω coaxial cable stub. CX24118A_N_2 Product data sheet m2 m1 Rev. 02 — 08 September 2009 Product data sheet 102322_015 © ...
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... Minimum Typical 0 +25 3.13 3.3 Conditions At 1 MSps (Pin = –81 dBm MSps (Pin = –70 dBm MSps (Pin = –65 dBm) Gain control voltage 0.5 to 2.5 V Single-ended Rev. 02 — 08 September 2009 CX24118A Units V V ° C ° C Maximum Units ° +70 C 3.47 V Min ...
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... Serial Interface Specifications High logic voltage Low logic voltage Specifications Rev. 02 — 08 September 2009 CX24118A Min Typ Max Units –30 dBc ±3 ±5 Deg. ±1 ± ...
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... LNB -- - PLL step size + + + offset 2.5 MHz. PLL step size, being very small (160 Hz), can be ignored. offset ÷ 2. Rev. 02 — 08 September 2009 CX24118A Min Typ Max Units 2330 4660 MHz 160 Hz 40 MHz –40 –30 dBc –44 –36 ...
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... NXP Semiconductors 5.3 Mechanical Specifications The CX24118A uses two 36-pin Quad Flat No-Lead (QFN) plastic packages. The CX24118A package diagrams are shown in Figure 11. Package Diagram D D1 Pin 1 Indicator TOP VIEW θ Seating Plane SIDE VIEW b CX24118A_N_2 Product data sheet Chapter 5: Electrical, Thermal, and Mechanical Specifications ...
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... 4.05 6.1 4.05 0.65 3.90 6.0 3.90 0 0.55 3.75 5.9 3.75 0.45 References JEDEC JEITA - - - - - - Rev. 02 — 08 September 2009 CX24118A SOT1092 detail 0.1 0.05 0.05 0.1 sot1092-2_po European Issue date projection 09-02-23 09-02-24 © NXP B.V. 2009. All rights reserved. 44 ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. Rev. 02 — 8 September 2009 CX24118A © NXP B.V. 2009. All rights reserved. 45 ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CX24118A All rights reserved. Date of release: 8 September 2009 Document identifier: CX24118A_N_2 ...