73S1209F Maxim, 73S1209F Datasheet - Page 44

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

1.7.5
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be
configured for counter or timer operations.
In timer mode, the register is incremented every machine cycle, meaning that it counts up after every 12
periods of the MPU clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input
signal T0 or T1 (T0 and T1 are the timer gating inputs derived from USR[0:7] pins, see the
Ports
rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure
proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers
and TCON) are used to select the appropriate mode.
The Timer 0 load registers are designated as TL0 and TH0 and the Timer 1 load registers are designated
as
Timer/Counter Mode Control Register (TMOD): 0x89
Bits TR1 and TR0 in the
44
TMOD.7
TMOD.3
TMOD.6
TMOD.2
TMOD.5
TMOD.1
TMOD.4
TMOD.0
TL1
Bit
section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count
and TH1.
Timers and Counters
MSB
GATE
Symbol
Gate
C/T
M1
M0
TCON
C/T
If set, enables external gate control (USR pin(s) connected to T0 or T1
for Counter 0 or 1, respectively). When T0 or T1 is high, and TRx bit is
set (see the
on T0 or T1 input pin. If not set, the TRx bit controls the corresponding
timer.
Selects Timer or Counter operation. When set to 1, the counter
operation is performed based on the falling edge of T0 or T1. When
cleared to 0, the corresponding register will function as a timer.
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in
the
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in
the
Timer 1
Table 41: TMOD Register Bit Description
register start their associated timers when set.
TMOD
TMOD
M1
Table 40: The TMOD Register
description.
description.
TCON
M0
register), a counter is incremented every falling edge
GATE
0x00
Function
C/T
Timer 0
M1
M0
LSB
User (USR)
(TMOD
Rev. 1.2