73S1209F Maxim, 73S1209F Datasheet - Page 39

• Manufacturer Part Number: 73S1209F
• Description: The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
• Manufacturer: Maxim

DS_1209F_004
1.7.4
The 80515 core of the 73S1209F includes two separate UARTs that can be programmed to communicate
with a host. The 73S1209F can only connect one UART at a time since there is only one set of TX and
Rx pins. The
UART has a different set of operating modes that the user can select according to their needs. The
UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at
up to 115,200 bits/s. The TX and RX pins operate at the V
exceed 3.6V. The operation of each pin is as follows:
RX: Serial input data is applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first.
The voltage applied at RX must not exceed 3.6V.
TX: This pin is used to output the serial data. The bytes are output LSB first.
The 73S1209F has several UART-related read/write registers. All UART transfers are programmable for
parity enable, parity select, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud
rates from 300 to 115200 bps. Table 33 shows the selectable UART operation modes and Table 34
shows how the baud rates are calculated.
Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit
output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1.8-bit
serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits
S0CON3 and S1CON3 in the S0COn and S1CON SFRs.
Note: S0REL (9:0) and S1REL (9:0) are 10-bit values derived by combining bits from the respective timer
reload registers SxRELH (bits 1:0) and SxRELL (bits 7:0). TH1 is the high byte of timer 1. The SMOD bit
is located in the
Rev. 1.2
Serial Interface 0
Serial Interface 1
Mode 0
Mode 1
Mode 2
Mode 3
UART
MISCtl0
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud rate
generator or timer 1)
baud rate (internal baud rate generator
Start bit, 8 data bits, stop bit, variable
fixed baud rate 1/32 or 1/64 of f
PCON
Start bit, 8 data bits, parity, stop bit,
register is used to select which UART is connected to the TX and RX pins. Each
SFR.
2
smod
* f
or timer 1)
UART 0
CKMPU
Using Timer 1
N/A
Table 34: Baud Rate Generation
/ (384 * (256-TH1))
N/A
Table 33: UART Modes
CKMPU
Start bit, 8 data bits, parity, stop bit, variable
Start bit, 8 data bits, stop bit, variable baud
DD
baud rate (internal baud rate generator)
Using Internal Baud Rate Generator
supply voltage levels and should never
rate (internal baud rate generator)
2
smod
f
CKMPU
* f
CKMPU
/(32 * (2
UART 1
/(64 * (2
N/A
N/A
10
73S1209F Data Sheet
-S1REL))
10
-S0REL))
39