ST10F273Z4 STMicroelectronics, ST10F273Z4 Datasheet - Page 181

• Manufacturer Part Number: ST10F273Z4
• Description: 16-BIT MICROCONTROLLER WITH MAC UNIT, UP TO 832 KBYTES FLASH MEMORY AND UP TO 68 KBYTES RAM
• Manufacturer: STMicroelectronics

Specifications of ST10F273Z4

• Single Voltage Supply: 5 V ±10%

ST10F273Z4
25.1.4
25.1.5
Spurious BREQ pulse in slave mode during external bus arbitration
phase
Description
Sporadic bus errors may occur when the device operates as a slave and the HOLD signal is
used for external bus arbitration.
After the slave has been granted the bus, it deactivates sporadically BREQ signal for a short
time, even though its access to the bus has not been completed. The master then starts
accessing the bus, thus causing a bus conflict between master and slave.
Workaround
To avoid producing any spurious BREQ pulse during slave external bus arbitrations, it is
necessary to ensure that the time between the HLDA assertion (Bus Acknowledge from
Master device) and the following HOLD falling edge (Bus Request from Master) is longer
than three clock cycles.
This can be achieved by delaying the HOLD signal with an RC circuit (see
Figure 63. Connecting an ST10 in slave mode
Executing PWRDN instructions
Description
The Power-down mode is not entered and the PWRDN instruction is ignored in the following
cases:
●
●
The PWRDN instruction is executed while NMI is high (PWDCFG bit of the SYSCON
register cleared)
The PWRDN instruction is executed while at least one of the Port 2 pins used to exit
from Power-down mode (PWDCFG bit of the SYSCON register is set) is at the active
level.
Master
HOLD
HLDA
BREQ
V
SS
BREQ (P6.7)
HOLD (P6.5)
HLDA (P6.6)
ST10 in Slave mode
Known limitations
Figure
63).
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