AD9726 Analog Devices, AD9726 Datasheet - Page 15

• Manufacturer Part Number: AD9726
• Manufacturer: Analog Devices

Specifications of AD9726

• Resolution (bits): 16bit
• Dac Update Rate: 400MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

SERIAL PORT INTERFACE
Table 8. SPI Register Map
Addr
0x00
0x02
0x0E
0x0F
0x10
0x11
0x15
0x16
Table 9. SPI Register Bit Default and Descriptions Values
Addr
0x00
0x02
0x0E
0x0F
Name
SDIODIR
DATADIR
SWRESET
SLEEP
PWRDWN
EXTREF
DATAFMT
DATARATE
INVDCLKI
INVDCLKO
DISDCLKO
SYNCMAN
SYNCUPD
SYNCALRM
CALMEM
CALCLK
SCALSTAT
SELFCAL
XFERSTAT
MEMXFER
SMEMWR
SMEMRD
FMEMRD
UNCAL
Bit 7
SDIODIR
DATAFMT
SCALSTAT
MEMADR[7]
Bits
7
6
5
4
3
0
7
6
5
4
3
2
1
0
[5:4]
[2:0]
7
6
5
4
3
2
1
0
Bit 6
DATADIR
DATARATE
SELFCAL
MEMADR[6]
BYPASS
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
I
O
I
O
I
I
I
I
I
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
000
0
0
0
0
0
0
0
0
Bit 5
SWRESET
INVDCLKI
CALMEM[1]
MEMADR[5]
MEMDAT[5]
SYNCEXT
XFERSTAT
Description
0: SDIO is input only (4-wire SPI mode), and SDO is used for output.
1: SDIO is input/output (3-wire SPI mode), and SDO is unused.
0: SPI serial data byte is MSB first format.
1: SPI serial data byte is LSB first format.
1: software reset: SPI registers (except 0x00) to default values.
1: analog outputs temporarily disabled.
1: full device power-down; all circuits disabled except SPI.
1: power-down internal reference; use external reference source.
0: input data-word is twos complement binary format.
1: input data-word is unsigned binary format.
0: DDR mode.
1: SDR mode.
1: inverts the polarity of the data clock input.
1: inverts the polarity of the data clock output.
1: disables the data clock output.
1: enables sync manual mode; disables automatic update.
1: forces manual sync update.
1: indicates that sync logic requires update.
2-bit SMEM contents and calibration status indicator.
00: uncalibrated; SMEM contains default values (63).
01: self-calibrated; SMEM contains values from self-calibration.
10: factory-calibrated; SMEM values are transferred from FMEM.
11: user-calibrated; SMEM contains user-entered values.
3-bit self-calibration clock divider ratio. Affects time available for algorithm settling. Each
value increase reduces time by 50%.
000: self-calibration clock is DAC clock/4096 (maximum self-calibration settling time for
highest linearity accuracy).
001,010,011: self-calibration clock is DAC clock/2048,1024,512.
100,101,110: self-calibration clock is DAC clock/256,128,64.
111: self-calibration clock is DAC clock/32 (minimum self-calibration settling time for
fastest algorithm completion).
1: indicates completion of self-calibration cycle.
1: initiates self-calibration cycle.
1: indicates completion of memory transfer cycle.
1: initiates FMEM to SMEM transfer.
1: enables static memory (SMEM) write operation.
1: enable sstatic memory (SMEM) read operation.
1: enables factory memory (FMEM) read operation.
1: enables uncalibrated operation; all SMEM to default values.
Bit 4
SLEEP
INVDCLKO
CALMEM[0]
MEMXFER
MEMADR[4]
MEMDAT[4]
SYNCIN[1]
Rev. B | Page 15 of 24
Bit 3
PWRDWN
DISDCLKO
SMEMWR
MEMADR[3]
MEMDAT[3]
SYNCIN[0]
4
5
3
Bit 2
SYNCMAN
CALCLK[2]
SMEMRD
MEMADR[2]
MEMDAT[2]
Bit 1
SYNCUPD
CALCLK[1]
FMEMRD
MEMADR[1]
MEMDAT[1]
SYNCOUT[1]
1
6
2
Bit 0
EXTREF
SYNCALRM
CALCLK[0]
UNCAL
MEMADR[0]
MEMDAT[0]
SYNCOUT[0]
AD9726