AD9726 Analog Devices, AD9726 Datasheet
AD9726
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AD9726 Summary of contents
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... All device operation is fully programmable using the flexible serial port interface (SPI). The AD9726 is also fully functional in its default state for applications without a controller. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...
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... AD9726 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 4 Digital Signal Specifications ........................................................ 5 Timing Specifications .................................................................. 5 Timing Diagrams .......................................................................... 6 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Terminology .................................................................................... 11 REVISION HISTORY 2/10— ...
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... MHz and MHz. DAC OUT Rev Page AD9726 = 20 mA, internal reference, Max Unit ±1.0 LSB ±2.5 LSB % MΩ 1.27 V μA V MΩ kHz ppm of FS/ºC ppm of FS/ºC ppm/º ...
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... AD9726 AC SPECIFICATIONS DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2 unless otherwise specified. MIN MAX Table 2. Parameter DYNAMIC PERFORMANCE Output Settling Time ( 0.1% ST Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) Output Noise ( mA) OUTFS TOTAL HARMONIC DISTORTION (THD 400 MHz, f ...
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... CLK± to IOUT Propagation Delay (t PD-BYPASS DB[15:0]± to IOUT Pipeline Delay (t PIPE-BYPASS Min 0.5 1.0 825 250 1.0 2.5 3.0 2.0 Min ) DCPD-DDR −100 500 ) DCPD-SDR −100 500 800 Rev Page AD9726 = 20 mA, internal reference, OUT-FS Typ Max Unit 1.0 V 1.25 V 1575 mV 100 mV 100 Ω 400 ...
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... AD9726 Parameter SERIAL PORT INTERFACE SCLK Frequency (f ) SCLK SCLK Rise/Fall Time SCLK Pulse Width High (t ) CPWH SCLK Pulse Width Low (t ) CPWL SCLK Setup Time (t ) CSU SDIO Setup Time (t ) DSU SDIO Hold Time ( SDIO/SDO Valid Time ( RESET PULSE WIDTH TIMING DIAGRAMS ...
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... Figure 5. Data Synchronization Bypass Pipeline Delay CSB SCLK SET-UP TIME t CSU SCLK PULSE WIDTH HIGH/LOW TIME t CPWH SCLK SDIO SET-UP TIME SDIO HOLD TIME t t DSU DH SDIO (SD0) Figure 6. SPI Timing Diagram Rev Page CPWL SDIO (SD0) VALID TIME t DV AD9726 ...
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... V to 3.6 V exposed package pad to an external heat sink (for example, the internal PCB copper ground plane). However, this is not necessary −0 2.8 V for the power dissipation and operating temperature range of the AD9726. −0 +0.3 V Table 6. Thermal Resistance −0 +0.3 V Package Type 80-Lead TQFP_EP Package, Thermally Enhanced − ...
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... Data Bit 7 True DB7− Data Bit 7 Complement DB6+ Data Bit 6 True DB6− Data Bit 6 Complement DB5+ Data Bit 5 True DB5− Data Bit 5 Complement DBVDD Data Bus Supply Voltage DBGND Data Bus Supply Common DB4+ Data Bit 4 True AD9726 ...
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... AD9726 Pin No. Mnemonic Description 43 DB4− Data Bit 4 Complement 44 DB3+ Data Bit 3 True 45 DB3− Data Bit 3 Complement 46 DB2+ Data Bit 2 True 47 DB2− Data Bit 2 Complement 48 DB1+ Data Bit 1 True 49 DB1− Data Bit 1 Complement 50 DB0+ Data Bit 0 True 51 DB0− ...
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... Noise Spectral Density (NSD) The measured noise power over bandwidth seen at the analog output. Total Harmonic Distortion (THD) The ratio in decibels of the rms power sum of the first six harmonic components to the rms power of the output signal. Rev Page AD9726 MIN ...
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... AD9726 TYPICAL PERFORMANCE CHARACTERISTICS 100 90 –6dB 80 –3dB 70 0dB (MHz) OUT Figure 8. SFDR vs 400 MSPS OUT 100 90 –6dB 80 0dB (MHz) OUT Figure 9. SFDR vs 200 MSPS OUT 100 0dB ...
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... MHz Figure 17. Four-Carrier WCDMA at 400 MSPS f OUT Rev Page AD9726 *ATTEN 6dB EXT REF SPAN 47.38MHz VBW 100kHz SWEEP 1.383s (601 pts) RRC FILTER: ON FILTER ALPHA 0.22 -20.72dBm/3.84000MHz LOWER UPPER ...
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... AD9726 REF –50dBm *ATTEN 2dB *AVG Log 10dB/ PAVG CENTER 70.00MHz *RES BW 10kHz VBW 100kHz SWEEP 2.451s (601 pts) TOTAL CARRIER POWER -20.62dBm/15.3600MHz RRC FILTER: ON FILTER ALPHA 0.22 REF CARRIER POWER -26.43dBm/3.84000MHz LOWER OFFSET FREQ INTEG BW dBc 5.000MHz 3.840MHz – ...
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... SMEM to default values. Rev Page Bit 2 Bit 1 SYNCMAN SYNCUPD CALCLK[2] CALCLK[1] SMEMRD FMEMRD MEMADR[2] MEMADR[1] MEMDAT[2] MEMDAT[1] SYNCOUT[ AD9726 Bit 0 EXTREF SYNCALRM CALCLK[0] UNCAL MEMADR[0] MEMDAT[0] SYNCOUT[0] ...
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... AD9726 Addr Name Bits I/O Default 0x10 MEMADR [7:0] I 00000000 0x11 MEMDAT [5:0] I/O 000000 0x15 SYNCOUT [1: 0x16 BYPASS SYNCEXT SYNCIN [4: SWRESET also resets itself. SMEM contents are unaffected by SWRESET; however, CALMEM reports an uncalibrated state. 2 EXTREF is optional because the internal reference circuit is designed to be overdriven by an external source. ...
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... The driver outputs are terminated as close as possible to the AD9726 with 50 Ω to VCC − (or use a Thevenin equivalent circuit). Controlled impedance PCB traces should be used to minimize reflections. Signal levels at the CLK+ and CLK– pins transition between a high near 1500 low near 750 mV. 0.1μ ...
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... For designs where multichip synchronization or fixed pipeline delay is important, the AD9726 can be configured to bypass the resynchronization circuitry and assure a fixed pipeline delay of four DAC clock cycles. In this mode, the data is sampled into the DAC using the DAC clock (CLK± ...
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... After reset, LVDS data can flow. The default state of the AD9726 is DDR and twos complement binary input data. To use the AD9726 in this mode not necessary to program any device registers. However, the SPI is enabled by default unless the SPI_DIS pin is connected high. If not disabled, SPI input pins should not be left floating ...
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... See the Sync Logic Operation and Programming section for a full explanation of sync opera- tional modes. SPI PIN DESCRIPTION The AD9726 SPI logic runs from the DBVDD supply rail, and input/output thresholds are based upon a nominal 3.3 V level. The maximum frequency of operation is 15 MHz. Chip Select (CSB) The CSB pin is an active low input ...
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... AD9726 output decreases. Gain CALDACs are an exception to this. Their contribution seen at the AD9726 output is in direct proportion to their binary input. Gain CALDACs are also half strength as compared to linearity CALDACs, but they are intended to be used together as a unit and thus, together, provide twice the current adjustment range ...
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... Harmonic products at integer multiples of the fundamental are thus revealed. This is the response using the AD9726 in an uncalibrated state. Figure 14 shows a response using the AD9726 in a calibrated state. Harmonic distortion due to the nonlinearities of the digital-to-analog conversion are virtually eliminated. SYNC LOGIC OPERATION AND PROGRAMMING ...
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... SYNCALRM status can then be monitored in hardware via the unused SPI pin SDO (54), and SYNCUPD requests can be entered in hardware via the unused SPI pin SCLK (56). If these two pins are connected together, fully automatic sync operation can be achieved. Rev Page AD9726 ...
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... Figure 24. 80-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP_EP] ORDERING GUIDE 1 Model Temperature Range AD9726BSVZ −40°C to +85°C AD9726BSVZRL −40°C to +85°C AD9726-EBZ RoHS Compliant Part. © 2005-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 14.20 14.00 SQ 12.20 13.80 1 ...