AD9148 Analog Devices, AD9148 Datasheet - Page 24

• Manufacturer Part Number: AD9148
• Manufacturer: Analog Devices

Specifications of AD9148

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9148
SPI REGISTER MAP
Table 12. Register Map
Addr
0x00
0x01
0x03
0x04
0x05
0x06
0x07
0x08
0x0A
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x14
0x15
0x17
0x18
0x19
0x1A
0x1C
0x1D
0x1E
Register
Name
Comm
Power
control
Data format
Interrupt
Enable 0
Interrupt
Enable 1
Event Flag 0
Event Flag 1
Clock
receiver
control
PLL Control 0
PLL Control 1
PLL Control 2
PLL Status 0
PLL Status 1
Sync Control 0
Sync Control 1
Sync Status 0
Data receiver
control
Data receiver
status
FIFO Status/
Control Port A
FIFO Status
Port A
FIFO Status/
Control Port B
FIFO Status
Port B
HB1 control
HB2 control
HB3 control
Bit 7
SDIO
direction
Power-
Down DAC
Set 1
Binary
format
Enable PLL
lock lost
PLL lock
lost
CLK duty
correction
PLL enable
Sync
enable
Sync lost
LVDS rcvr
frame high
FIFO
Warning 1
FIFO
Warning 1
Enable
pre mod
Bypass
digital gain
and phase
adjustment
PLL Loop Bandwidth[2:0]
N2[1:0]
Bit 6
LSB/
MSB first
Power-
Down
DAC Set 2
Q first
enable
Enable
PLL lock
PLL lock
REFCLK
duty
correction
PLL
manual
enable
FIFO rate/
data rate
toggle
Sync
locked
One DCI
LVDS rcvr
frame low
FIFO
Warning 2
FIFO
Warning 2
Bypass
sinc
−1
Bit 5
Software
reset
Power-
down data
receiver
Dual-port
mode
Enable
sync
lock lost
Sync lock
lost
CLK cross
correction
LVDS rcvr
DCI high
FIFO reset
aligned
FIFO reset
aligned
Rev. B | Page 24 of 72
Bit 4
DAC SPI
select
Bus swap
Enable
sync lock
Enable AED
compare pass
Sync lock
AED compare
pass
REFCLK cross
correction
0
PLL cross
control enable
LVDS rcvr
DCI low
FIFO SPI
align ack
FIFO SPI
align ack
FIFO Level[7:0]
FIFO Level[7:0]
VCO Band Readback[5:0]
Sync Phase Request[5:0]
Bit 3
Byte mode
Enable AED
compare
fail
AED
compare
fail
0
1
Rising
edge sync
LVDS rcvr
Port B high
FIFO SPI
align
requesting
FIFO SPI
align
requesting
Manual VCO Band[5:0]
N0[1:0]
PLL Control Voltage[3:0]
HB2[2:0]
HB3[2:0]
Bit 2
Byte
swap
Enable
FIFO SPI
aligned
Enable
SED
compare
fail
FIFO SPI
aligned
SED
compare
fail
1
0
LVDS rcvr
Port B low
HB1[1:0]
FIFO Phase Offset[2:0]
FIFO Phase Offset[2:0]
Sync Averaging[2:0]
Bit 1
Enable
FIFO
Warning 1
FIFO
Warning 1
1
0
LVDS rcvr
Port A
high
N1[1:0]
Bit 0
Enable
FIFO
Warning 2
FIFO
Warning 2
1
1
LVDS rcvr
Port A low
Bypass
HB1
Bypass
HB2
Bypass
HB3
Data Sheet
Default
0x00
0x00
0x20
0x00
0x00
0x37
0x40
0xF1
0xD9
0x08
0x00
0x00
0x00
0x00
0x40
0x00
0x81