AD9148 Analog Devices, AD9148 Datasheet - Page 13

• Manufacturer Part Number: AD9148
• Manufacturer: Analog Devices

Specifications of AD9148

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
Pin No.
C14
D14
C2
D2
B3
B4
B11
B12
C13
D13
A8
A7
B6, A6
B9, A9
H4
H3
G1
G2
H1
H2
G11, G12
H12
G13
G14
H13
H14
M1, L1
P1, N1
M2, L2
P2, N2
P3, N3
P4, N4
P5, N5
P6, N6
P7, N7
P8, N8
P9, N9
P10, N10
P11, N11
P12, N12
P13, N13
P14, N14
K13, J13
K14, J14
K3, J3
M3, L3
K4, J4
M4, L4
M5, L5
M6, L6
Mnemonic
IOUT4_N
IOUT4_P
AUX1_N
AUX1_P
AUX2_N
AUX2_P
AUX3_P
AUX3_N
AUX4_N
AUX4_P
I120
VREF
CLK_P/CLK_N
REFCLK_P/REFCLK_N or
SYNC_P/SYNC_N
IRQ
RESET
SDO
CS
SDIO
SCLK
TRENCH
PLL_LOCK
TMS
TDI
TCK
TDO
A0_P/A0_N
A1_P/A1_N
A2_P/A2_N
A3_P/A3_N
A4_P/A4_N
A5_P/A5_N
A6_P/A6_N
A7_P/A7_N
A8_P/A8_N
A9_P/A9_N
A10_P/A10_N
A11_P/A11_N
A12_P/A12_N
A13_P/A13_N
A14_P/A14_N
A15_P/A15_N
DCIA_P/DCIA_N
FRAMEA_P/FRAMEA_N
B0_P/B0_N
B1_P/B1_N
B2_P/B2_N
B3_P/B3_N
B4_P/B4_N
B5_P/B5_N
Rev. B | Page 13 of 72
Description
DAC 4 Complementary Output Current.
DAC 4 Positive Output Current.
Auxiliary DAC 1 Complementary Output Current.
Auxiliary DAC 1 Positive Output Current.
Auxiliary DAC 2 Complementary Output Current.
Auxiliary DAC 2 Positive Output Current.
Auxiliary DAC 3 Positive Output Current.
Auxiliary DAC 3 Complementary Output Current.
Auxiliary DAC 4 Complementary Output Current.
Auxiliary DAC 4 Positive Output Current.
Tie to analog ground via a 10 kΩ resistor to generate a 120 µA reference current.
Band Gap Voltage Reference I/O. Decouple to analog ground via a 0.1 µF
capacitor. Output impedance is approximately 5 kΩ.
Positive/Negative DAC Clock Input (CLK).
PLL Reference Clock Input (REFCLK_x). This pin has a secondary function as
a synchronization input (SYNC_x).
Active Low Open-Drain Interrupt Request Output. Pull up to IOVDD with
a 10 kΩ resistor.
An active low LVCMOS input resets the device. Pull up to IOVDD.
Serial Data Output for SPI.
Active Low Chip Select for SPI.
Serial Data Input/Output for SPI.
Qualifying Clock Input for SPI.
Connect this pin to VSS.
Active High LVCMOS Output. It indicates the lock status of the PLL circuitry.
Reserved for Future Use. Connect to DVSS.
Reserved for Future Use. Connect to DVSS.
Reserved for Future Use. Connect to DVSS.
Reserved for Future Use. Leave unconnected.
LVDS Data Input Pair, Port A (LSB).
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A.
LVDS Data Input Pair, Port A (MSB).
LVDS Data Clock Input Pair for Port A.
LVDS Frame Input for Port A. Tie to LVDS logic low if not used.
Recommended external bias circuit is shown in Figure 49.
LVDS Data Input Pair, Port B (LSB).
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B.
LVDS Data Input Pair, Port B
LVDS Data Input Pair, Port B.
AD9148