AD7720 Analog Devices, AD7720 Datasheet - Page 6

• Manufacturer Part Number: AD7720
• Description: CMOS Sigma-Delta Modulator with 90 dB Dynamic Range
• Manufacturer: Analog Devices

Specifications of AD7720

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 25MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (Vref) p-p,2.5V p-p,Uni (Vref),Uni 2.5V
• Adc Architecture: Sigma-Delta Modulator
• Pkg Type: SOP

AD7720
Pin No.
1
2, 14, 18, 20, 24, 26 AGND
3, 13
4
5
6, 15
7
8
9
10
11
12
16
17
19
21, 23
25, 28
22
27
Mnemonic
REF2
NC
STBY
DVAL
DGND
GC
BIP
MZERO
DATA
SCLK
RESETO
XTAL1/MCLK CMOS Logic Clock Input. The XTAL1/MCLK pin interfaces the device’s internal oscillator
XTAL2
DVDD
VIN(–), VIN(+) Analog Input. In unipolar operation, the analog input range on VIN(+) is VIN(–) to
AVDD
RESET
REF1
Function
Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used
to drive the sigma-delta modulator. When REF2 is used as an input, REF1 must be con-
nected to AGND.
Ground reference point for analog circuitry.
No Connect.
Standby, Logic Input. When STBY is high, the device is placed in a low power mode.
When STBY is low, the device is powered up.
Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from
the AD7720 is an accurate digital representation of the analog voltage at the input to the
sigma-delta modulator. The DVAL pin is set low for 20 MCLK cycles if the analog input is
overranged.
Ground reference for the digital circuitry.
Digital Control Input. When GC is high, the gain error of the modulator can be calibrated.
Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A
logic high selects bipolar mode.
Digital Control Input. When MZERO is high, the modulator inputs are internally grounded,
i.e., tied to AGND in unipolar mode and REF2 in bipolar mode. MZERO allows on-chip
offsets to be calibrated out. MZERO is low for normal operation.
Modulator Bit Stream. The digital bit stream from the sigma-delta modulator is output at
DATA.
Serial Clock, Logic Output. The bit stream from the modulator is valid on the rising edge
of SCLK.
Reset Logic Output. The signal applied to the RESET pin is made available as an output at
RESETO.
circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency,
microprocessor-grade crystal and a 1 M resistor should be connected between the MCLK
and XTAL pins with two capacitors connected from each pin to ground. Alternatively, the
XTAL1/MCLK pin can be driven with an external CMOS-compatible clock. The part is
specified with a 12.5 MHz master clock.
Oscillator Output. The XTAL2 pin connects the internal oscillator output to an external
crystal. If an external clock is used, XTAL2 should be left unconnected.
Digital Supply Voltage, +5 V
(VIN(–) + V
The absolute analog input range must lie between 0 and AVDD. The analog input is con-
tinuously sampled and processed by the analog modulator.
Analog Positive Supply Voltage, +5 V
Reset Logic Input. RESET is an asynchronous input. When RESET is taken high, the
sigma-delta modulator is reset by shorting the integrator capacitors in the modulator. DVAL
goes low for 20 MCLK cycles while the modulator is being reset.
Reference Input/Output. REF1 connects via a 3 k resistor to the output of the internal
2.5 V reference, and to the input of a buffer amplifier that drives the sigma-delta modulator.
This pin can also be overdriven with an external 2.5 V reference.
PIN FUNCTION DESCRIPTIONS
REF
); for bipolar operation, the analog input range on VIN+ is (VIN(–)
–6–
5%.
5%.
V
REF
REV. 0
/2).