AD7720 Analog Devices, AD7720 Datasheet

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AD7720

Manufacturer Part Number
AD7720
Description
CMOS Sigma-Delta Modulator with 90 dB Dynamic Range
Manufacturer
Analog Devices
Datasheet

Specifications of AD7720

Resolution (bits)
16bit
# Chan
1
Sample Rate
25MSPS
Interface
Ser
Analog Input Type
Diff-Bip,Diff-Uni
Ain Range
(Vref) p-p,2.5V p-p,Uni (Vref),Uni 2.5V
Adc Architecture
Sigma-Delta Modulator
Pkg Type
SOP

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a
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
GENERAL DESCRIPTION
This device is a 7th order sigma-delta modulator that converts
the analog input signal into a high speed 1-bit data stream. The
part operates from a +5 V supply and accepts a differential input
range of 0 V to +2.5 V or 1.25 V centered about a common-
mode bias. The analog input is continuously sampled by the
analog modulator, eliminating the need for external sample and
hold circuitry. The input information is contained in the output
stream as a density of ones. The original information can be
reconstructed with an appropriate digital filter.
The part provides an accurate on-chip 2.5 V reference. A refer-
ence input/output function is provided to allow either the inter-
nal reference or an external system reference to be used as the
reference source for the part.
The device is offered in a 28-lead TSSOP package and designed
to operate from –40 C to +85 C.
FEATURES
12.5 MHz Master Clock Frequency
0 V to +2.5 V or
Single Bit Output Stream
90 dB Dynamic Range
Power Supplies: AVDD, DVDD: +5 V
On-Chip 2.5 V Voltage Reference
28-Lead TSSOP
1.25 V Input Range
5%
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
MZERO
VIN(+)
VIN(–)
STBY
BIP
GC
CMOS Sigma-Delta Modulator
AVDD
FUNCTIONAL BLOCK DIAGRAM
AD7720
AGND
CONTROL
SIGMA-DELTA
MODULATOR
LOGIC
World Wide Web Site: http://www.analog.com
DVDD
DGND
REFERENCE
© Analog Devices, Inc., 1997
CIRCUITRY
CLOCK
REF1
2.5V
AD7720
REF2
DATA
SCLK
DVAL
RESETO
RESET
XTAL1/MCLK
XTAL2

Related parts for AD7720

AD7720 Summary of contents

Page 1

... VIN(–) MZERO GC BIP STBY One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 AD7720 AGND DVDD DGND REF1 AD7720 2.5V REFERENCE SIGMA-DELTA MODULATOR CLOCK CIRCUITRY CONTROL LOGIC World Wide Web Site: http://www.analog.com © Analog Devices, Inc., 1997 REF2 DATA ...

Page 2

... AD7720–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution Differential Nonlinearity Integral Nonlinearity Precalibration Offset Error 2 Precalibration Gain Error 3 Postcalibration Offset Error 2, 3 Postcalibration Gain Error Offset Error Drift Gain Error Drift Unipolar Mode Bipolar Mode ANALOG INPUTS Signal Input Span (VIN(+) – VIN(–)) ...

Page 3

... V min/V max 4.75/5.25 V min/V max Digital Inputs Equal DVDD 43 mA max 25 A max 90.625kHz DECIMATE BY 32 120dB 292.969kHz FILTER 2 BANDWIDTH = 90.625 kHz TRANSITION = 104.687kHz ATTENUATION = 90dB COEFFICIENTS = 151 –3– | 200 A OUT | 1.6 mA OUT DECIMATE 16-BIT BY 2 OUTPUT 90dB 104.687kHz AD7720 ...

Page 4

... AD7720 TIMING CHARACTERISTICS Limit at T MIN Parameter (B Version) f 100 MCLK 0. MCLK t 0. MCLK MCLK NOTE Guaranteed by design. Figure 2. Load Circuit for Access Time and Bus Relinquish Time SCLK (O) DATA (O) NOTE: O SIGNIFIES AN OUTPUT ...

Page 5

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7720 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 6

... When STBY is low, the device is powered up. Data Valid Logic Output. A logic high on DVAL indicates that the data bit stream from the AD7720 is an accurate digital representation of the analog voltage at the input to the sigma-delta modulator. The DVAL pin is set low for 20 MCLK cycles if the analog input is overranged ...

Page 7

... TERMINOLOGY (IDEAL FIR FILTER USED WITH AD7720 [FIGURE 1]) Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (not to be con- fused with bipolar zero), a point 0.5 LSB below the first code transition (100 ...

Page 8

... AD7720–Typical Characteristics (AVDD = DVDD = 5 +25 C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode noted) 110 100 90 SFDR 80 S/ (N+ –40 –30 –20 –10 0 INPUT LEVEL – dB Figure 5. S/(N+D) and SFDR vs. Analog Input Level –85 –90 SNR V (+) = V (–) = 1.25Vpk– – ...

Page 9

... AD7720 65535 FREQUENCY – kHz 70E+3 80E+3 Figure 19. 16K Point FFT 70E+3 80E+3 Figure 20. 16K Point FFT 393.295 kHz 90E+3 98E+3 90E+3 96E+3 ...

Page 10

... To remedy the situation, a low pass MCLK RC filter can be connected between the amplifier and the input to the AD7720 as shown in Figure 23. The external capacitor at each input aids in supplying the current spikes created during the sampling process. The resistor in this diagram, as well as creating the pole for the antialiasing, isolates the op amp from the transient nature of the load ...

Page 11

... VIN(+) pin to form a differential signal around an initial bias voltage of 1.25 V. For single-ended applications, best THD performance is obtained with VIN(–) set to 1.25 V rather than 2.5 V. The input to the AD7720 can also be driven differen- tially with a complementary input as shown in Figure 29. SWITCHED-CAP DAC REF In this case, the input common-mode voltage is set to 2 ...

Page 12

... REF1 multipurpose system clock that is generated on the digital ground plane. If the clock signal is passed between its origin on a digital plane to the AD7720 on the analog ground plane, the REF2 ground noise between the two planes adds directly to the clock and will produce excess jitter. The jitter can cause unwanted degradation in the signal-to-noise ratio and also produce un- wanted harmonics ...

Page 13

... Digital and analog ground planes should only be joined in one place. If the AD7720 is the only device requir- ing an AGND-to-DGND connection, the ground planes should be connected at the AGND and DGND pins of the AD7720. ...

Page 14

... AD7720 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Thin Shrink Small Outline (RU-28) 0.386 (9.80) 0.378 (9.60 PIN 1 0.0433 (1.10) MAX 0.0118 (0.30) 0.0256 (0.65) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) –14– 0.028 (0.70 0.020 (0.50) REV. 0 ...

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