AD7720 Analog Devices, AD7720 Datasheet - Page 2

• Manufacturer Part Number: AD7720
• Description: CMOS Sigma-Delta Modulator with 90 dB Dynamic Range
• Manufacturer: Analog Devices

Specifications of AD7720

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 25MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (Vref) p-p,2.5V p-p,Uni (Vref),Uni 2.5V
• Adc Architecture: Sigma-Delta Modulator
• Pkg Type: SOP

AD7720–SPECIFICATIONS
Parameter
STATIC PERFORMANCE
ANALOG INPUTS
REFERENCE INPUTS
DYNAMIC SPECIFICATIONS
CLOCK
Resolution
Differential Nonlinearity
Integral Nonlinearity
Precalibration Offset Error
Precalibration Gain Error
Postcalibration Offset Error
Postcalibration Gain Error
Offset Error Drift
Gain Error Drift
Signal Input Span (VIN(+) – VIN(–))
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
Differential Input Impedance
REF1 Output Voltage
REF1 Output Voltage Drift
REF1 Output Impedance
Reference Buffer Offset Voltage
Using Internal Reference
Using External Reference
Bipolar Mode
Signal to (Noise + Distortion)
Unipolar Mode
Intermodulation Distortion
AC CMRR
Overall Digital Filter Response
MCLK Duty Ratio
V
V
External Reference Voltage Range
MCLKH
MCLKL
Unipolar Mode
Bipolar Mode
Bipolar Mode
Unipolar Mode
REF2 Output Voltage
REF2 Output Voltage Drift
REF2 Input Impedance
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal to (Noise + Distortion)
Total Harmonic Distortion
Spurious Free Dynamic Range
0 kHz–90.625 kHz
96.92 kHz
104.6875 kHz to 12.395 MHz
, MCLK Low Voltage
, MCLK High Voltage
2
2, 3
3
5
5
5
4
5
B Version
16
0 to V
AVDD
0
2
2 f
10
2.32 to 2.62
60
3
2.32 to 2.62
60
10
2.32 to 2.62
90
86/84.5
–90/–88
–90
88
84.5/83
–89/–87
–90
–93
96
–3
90
45 to 55
4
0.4
1
2
6
0.6
1.5
0.3
1
1
0.5
V
12
0.005
9
9
MCLK
REF2
/(8 f
/(16 f
REF2
/2
MCLK
1
MCLK
(AVDD = +5 V
REF2 = +2.5 V; T
)
)
Units
Bits
LSB max
LSB typ
mV typ
% FSR typ
mV typ
% FSR typ
LSB/ C typ
LSB/ C typ
LSB/ C typ
V max
V max
V
V
pF typ
MHz
k typ
V min/max
ppm/ C typ
k typ
mV max
V min/max
ppm/ C typ
k typ
V min/max
dB typ
dB min
dB max
dB max
dB typ
dB min
dB max
dB max
dB typ
dB typ
dB max
dB min
dB typ
% max
V min
V max
–2–
A
5%; DVDD = +5 V
= T
MIN
to T
Test Conditions/Comments
When Tested with Ideal FIR Filter as in Figure 1
Guaranteed Monotonic
REF2 Is an Ideal Reference, REF1 = AGND
BIP = V
BIP = V
Offset Between REF1 and REF2
REF1 = AGND
Applied to REF1 or REF2
When Tested with Ideal FIR Filter as in Figure 1
BIP = V
or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V
Input BW = 0 kHz–90.625 kHz
Input BW = 0 kHz–90.625 kHz
Input BW = 0 kHz–90.625 kHz
BIP = V
Input BW = 0 kHz–90.625 kHz
Input BW = 0 kHz–97.65 kHz
Input BW = 0 kHz–97.65 kHz
VIN(+) = VIN(–) = 2.5 V p-p, V
3.75 V, 20 kHz
See Figure 1 for Characteristics of FIR Filter
For Specified Operation
MCLK Uses CMOS Logic
MIN
, unless otherwise noted)
IH
IH
IL
IL
, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V
, V
5%; AGND = DGND = 0 V, f
CM
= 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p
CM
= 1.25 V to
MCLK
= 12.5 MHz,
REV. 0