AD7709 Analog Devices, AD7709 Datasheet - Page 24

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AD7709

Manufacturer Part Number
AD7709
Description
16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port
Manufacturer
Analog Devices
Datasheet

Specifications of AD7709

Resolution (bits)
16bit
# Chan
4
Sample Rate
n/a
Interface
Ser,SPI
Analog Input Type
Diff-Uni,SE-Uni
Ain Range
(2Vref/PGA Gain) p-p
Adc Architecture
Sigma-Delta
Pkg Type
SOP

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AD7709
When the ADC is configured for bipolar operation, the coding
is offset binary with a negative full-scale voltage resulting in a
code of 000 . . . 000, a zero differential voltage resulting in a
code of 100 . . . 000, and a positive full-scale voltage resulting in
a code of 111 . . . 111. The output code from the ADC for any
analog input voltage can be represented as follows:
where:
Excitation Currents
The AD7709 also contains three software configurable constant
current sources. IEXC1 and IEXC2 provide 200 mA of current
while IEXC3 provides 25 mA of current. All source current
from V
device. These current sources are controlled via bits in the
Configuration Register. The configuration bits enable the current
sources, and they can be configured to source current individually
to both pins or a combination of currents, i.e., 400 mA, 225 mA, or
425 mA to either of the selected output pins. These current sources
can be used to excite external resistive bridge or RTD sensors.
Crystal Oscillator
The AD7709 is intended for use with a 32.768 kHz watch crys-
tal. A PLL internally locks onto a multiple of this frequency to
provide a stable 4.194304 MHz clock for the ADC. The modu-
lator sample rate is the same as the crystal oscillator frequency.
The start-up time associated with 32.768 kHz crystals is typically
300 ms. The OSCPD bit in the Communications Register can
be used to prevent the oscillator from powering down when the
AD7709 is placed in power-down mode. This avoids having to
wait 300 ms after exiting power-down to start a conversion at the
expense of raising the power-down current.
Reference Input
The AD7709 has a fully differential reference input capability
for the channel. On the channel, the reference inputs can be
REFIN1(+) and REFIN1(–) or REFIN2(+) and REFIN2(–).
They provide a differential reference input capability. The
common-mode range for these differential inputs is from GND
to V
excessive R-C source impedances will introduce gain errors.
The nominal reference voltage, V
– REFIN1(–) or (REFIN2(+) – REFIN2(–)), for specified
operation is 2.5 V, but the AD7709 is functional with reference
voltages from 1 V to V
(voltage or current) for the transducer on the analog input also
drives the reference voltage for the part, the effect of the low
frequency noise in the excitation source will be removed
AIN is the analog input voltage.
GAIN in the PGA gain, i.e., 1 on the ± 2.56 V range and 128
on the ± 20 mV range.
N = 16.
DD
Code
DD
. The reference input is unbuffered and therefore
is directed to either the IOUT1 or IOUT2 pins of the
=
2
N
-
1
¥
[
(
AIN
DD
. In applications where the excitation
¥
GAIN
REF
/ .
(
1 024
, ((REFIN1(+)
¥
V
REF
)
)
+
1
]
–24–
because the application is ratiometric. If the AD7709 is used
in a nonratiometric application, a low noise reference should be
used. Recommended reference voltage sources for the AD7709
include the AD780, REF43, and REF192. It should also be noted
that the reference inputs provide a high impedance, dynamic load.
Because the input impedance of each reference input is dynamic,
resistor/capacitor combinations on these inputs can cause dc gain
errors, depending on the output impedance of the source that is
driving the reference inputs. Reference voltage sources like those
recommended above (e.g., AD780) will typically have low output
impedances and are therefore tolerant to having decoupling capaci-
tors on the REFIN(+) without introducing gain errors in the system.
Deriving the reference input voltage across an external resistor, as
shown in Figure 18, will mean that the reference input sees a
significant external source impedance. External decoupling on the
REFIN pins would not be recommended in this type of circuit
configuration.
Reset Input
The RESET input on the AD7709 resets all the logic, the digital
filter, and the analog modulator while all on-chip registers are reset
to their default state. RDY is driven high and the AD7709 ignores
all communications to any of its registers while the RESET
input is low. When the RESET input returns high, the AD7709
operates with its default setup conditions and it is necessary to
set up all registers after a RESET command.
Power-Down Mode
Loading 0 to the STBY bit in the ADC Communications Register
places the AD7709 in device power-down mode. The AD7709
retains the contents of all its on-chip registers (including the data
register) while in power-down mode.
The device power-down mode does not affect the digital interface,
but it does affect the status of the RDY pin. Putting the AD7709
into power-down mode will reset the RDY line high. Placing the
part in power-down mode reduces the total current to 26 mA
typical when the part is operated at 5 V with the oscillator running
during power-down mode. With the oscillator shut down, the total
I
Grounding and Layout
Since the analog inputs and reference inputs on the ADC are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode rejection
of the part will remove common-mode noise on these inputs.
The digital filter will provide rejection of broadband noise on
the power supply, except at integer multiples of the modulator
sampling frequency. The digital filter also removes noise from
the analog and reference inputs, provided these noise sources do
not saturate the analog modulator. As a result, the AD7709 is
more immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD7709 is so high, and the noise levels from the AD7709 so
low, care must be taken with regard to grounding and layout.
DD
is 1.5 mA typical at 3 V and 6.5 mA typical at 5 V.
REV. A

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