AD7709 Analog Devices, AD7709 Datasheet - Page 21

• Manufacturer Part Number: AD7709
• Description: 16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port
• Manufacturer: Analog Devices

Specifications of AD7709

• Resolution (bits): 16bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7709-to-68HC11 Interface
Figure 11 shows an interface between the AD7709 and the
68HC11 microcontroller. The diagram shows the minimum
(3-wire) interface with CS on the AD7709 hardwired low. In this
scheme, the RDY bit of the Status Register is monitored to
determine when the Data Register is updated. An alternative
scheme, which increases the number of interface lines to four, is to
monitor the RDY output line from the AD7709. The monitoring
of the RDY line can be done in two ways. First, RDY can be
connected to one of the 68HC11 port bits (such as PC0), which
is configured as an input. This port bit is then polled to determine
the status of RDY. The second scheme is to use an interrupt
driven system, in which case the RDY output is connected to
the IRQ input of the 68HC11. For interfaces that require
control of the CS input on the AD7709, one of the port bits of the
68HC11 (such as PC1), which is configured as an output, can
be used to drive the CS input.
The 68HC11 is configured in the master mode with its CPOL
bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the
68HC11 is configured like this, its SCLK line idles high between
data transfers. The AD7709 is not capable of full-duplex opera-
tion. If the AD7709 is configured for a write operation, no data
appears on the DOUT lines even when the SCLK input is active.
Similarly, if the AD7709 is configured for a read operation, data
presented to the part on the DIN line is ignored even when
SCLK is active.
AD7709-to-8051 Interface
An interface circuit between the AD7709 and the 8XC51 microcon-
troller is shown in Figure 12. The diagram shows the minimum
number of interface connections with CS on the AD7709 hard-
wired low. In the case of the 8XC51 interface, the minimum
number of interconnects is just two. In this scheme, the RDY
bit of the Status Register is monitored to determine when the
Data Register is updated. The alternative scheme, which increases
the number of interface lines to three, is to monitor the RDY output
line from the AD7709. The monitoring of the RDY line can be
done in two ways. First, RDY can be connected to one of the
8XC51 port bits (such as P1.0) which is configured as an input.
This port bit is then polled to determine the status of RDY.
REV. A
Figure 11. AD7709-to-68HC11 Interface
68HC11
MISO
MOSI
SCK
SS
V
DD
V
DD
RESET
SCLK
DOUT
DIN
CS
AD7709
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The second scheme is to use an interrupt-driven system, in which
case the RDY output is connected to the INT1 input of the
8XC51. For interfaces that require control of the CS input on
the AD7709, one of the port bits of the 8XC51 (such as P1.1),
which is configured as an output, can be used to drive the CS
input. The 8XC51 is configured in its Mode 0 serial interface
mode. Its serial interface contains a single data line. As a result,
the DOUT and DIN pins of the AD7709 should be connected
together with a 10 kW pull-up resistor. The serial clock on the
8XC51 idles high between data transfers. The 8XC51 outputs
the LSB first in a write operation, while the AD7709 expects the
MSB first so the data to be transmitted has to be rearranged
before being written to the output serial register. Similarly, the
AD7709 outputs the MSB first during a read operation while
the 8XC51 expects the LSB first. Therefore, the data read into
the serial buffer needs to be rearranged before the correct data
word from the AD7709 is available in the accumulator.
AD7709-to-ADSP-2103/ADSP-2105 Interface
Figure 13 shows an interface between the AD7709 and the
ADSP-2103/ADSP-2105 DSP processor. In the interface shown,
the RDY bit of the Status Register is again monitored to
determine when the Data Register is updated. The alternative
scheme is to use an interrupt-driven system, in which case the
Figure 13. AD7709-to-ADSP-2103/ADSP-2105 Interface
Figure 12. AD7709-to-8XC51 Interface
ADSP-2103/
ADSP-2105
8XC51
SCLK
P3.0
P3.1
RFS
TFS
DR
DT
V
DD
10k
V
V
DD
DD
RESET
DOUT
DIN
SCLK
CS
RESET
CS
DOUT
DIN
SCLK
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