AD7655 Analog Devices, AD7655 Datasheet - Page 6

• Manufacturer Part Number: AD7655
• Manufacturer: Analog Devices

Specifications of AD7655

• Resolution (bits): 16bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7655
Parameter
SLAVE SERIAL INTERFACE MODES (See Figure 31 and Figure 32)
1
2
Table 4. Serial Clock Timings in Master Read After Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Typical
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
Symbol
t
t
t
t
t
t
t
t
t
t
25
26
26
27
28
29
30
31
35
35
Rev. B | Page 6 of 28
0
0
3
25
40
12
7
4
2
1
3.25
3.5
L
Symbol
t
t
t
t
t
t
t
of 10 pF; otherwise C
38
39
40
41
42
43
44
0
1
17
50
70
22
21
18
4
3
4.25
4.5
Min
5
3
5
5
25
10
10
1
0
17
100
140
50
49
18
30
30
6.25
6.5
L
is 60 pF maximum.
Typ
1
1
17
200
280
100
99
18
80
80
10.75
11
Max
18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
Unit
ns
ns
ns
ns
ns
ns
ns