AD7655 Analog Devices, AD7655 Datasheet - Page 20

• Manufacturer Part Number: AD7655
• Manufacturer: Analog Devices

Specifications of AD7655

• Resolution (bits): 16bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7655
SERIAL INTERFACE
The AD7655 is configured to use the serial interface when the
SER/ PAR is held high. The AD7655 outputs 32 bits of data, MSB
first, on the SDOUT pin. The order of the channels being output
is also controlled by A/ B . When high, Channel A is output first;
when low, Channel B is output first. This data is synchronized
with the 32 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7655 is configured to generate and provide the serial
data clock SCLK when the EXT/ INT pin is held low. The
AD7655 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted, if desired, using the INVSCLK
and INVSYNC inputs, respectively. The output data is valid on
both the rising and falling edge of the data clock. In this mode,
the D7/RDC/SDIN input is used to select between reading after
conversion (RDC = low) or reading previous conversion results
during conversion (RDC = high). Figure 28 and Figure 29 show
the detailed timing diagrams of these two modes.
Rev. B | Page 20 of 28
Usually, because the AD7655 is used with a fast throughput, the
master read during convert mode is the most recommended
serial mode when it can be used. In this mode, the serial clock
and data toggle at appropriate instants, which minimizes
potential feed through between digital activity and the critical
conversion decisions. The SYNC signal goes low after the LSB
of each channel has been output. Note that in this mode, the
SCLK period changes because the LSBs require more time to
settle, and the SCLK is derived from the SAR conversion clock.
Note that in master read after convert mode, unlike in other
modes, the BUSY signal returns low after the 32 bits of data are
pulsed out and not at the end of the conversion phase, which
results in a longer BUSY width. One advantage of using this
mode is that it can accommodate slow digital hosts because the
serial clock can be slowed down by using the DIVSCLK[1:0]
inputs. Refer to Table 4 for the timing details.