AD7655 Analog Devices, AD7655 Datasheet - Page 24

no-image

AD7655

Manufacturer Part Number
AD7655
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7655

Resolution (bits)
16bit
# Chan
4
Sample Rate
1MSPS
Interface
Par,Ser,SPI
Analog Input Type
SE-Uni
Ain Range
Uni (Vref) x 2
Adc Architecture
SAR
Pkg Type
CSP,QFP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD7655AST
Manufacturer:
ADI
Quantity:
300
Part Number:
AD7655ASTZ
Manufacturer:
ADI
Quantity:
2
Part Number:
AD7655ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7655ASTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD7655ASTZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD7655SCP-EP-RL
Manufacturer:
CYPRESS
Quantity:
210
Part Number:
AD7655SCPZ-EP-RL
Manufacturer:
MICROCHIP
Quantity:
1 000
AD7655
MICROPROCESSOR INTERFACING
The AD7655 is ideally suited for traditional dc measurement
applications supporting a microprocessor and for ac signal
processing applications interfacing to a digital signal processor.
The AD7655 is designed to interface with either a parallel
8-bit-wide or 16-bit-wide interface, a general-purpose serial port,
or I/O ports on a microcontroller. A variety of external buffers
can be used with the AD7655 to prevent digital noise from
coupling into the ADC. The following section describes the use of
the AD7655 with an SPI-equipped DSP, the ADSP-219x.
SPI INTERFACE (ADSP-219
Figure 33 shows an interface diagram between the AD7655 and
the SPI1-equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7655 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature to be used. The convert command can be initiated
in response to an internal timer interrupt. The 32-bit output
data is read with two serial peripheral interface (SPI) 16-bit
wide accesses. The reading process can be initiated in response
X
)
Rev. B | Page 24 of 28
to the end of conversion signal (BUSY going low) using an
interrupt line of the DSP. The SPI on the ADSP-219x is
configured for master mode—(MSTR) = 1, Clock Polarity bit
(CPOL) = 0, Clock Phase bit (CPHA) = 1, and SPI Interrupt
Enable (TIMOD) = 00—by writing to the SPI control register
(SPICLTx). To meet all timing requirements, the SPI clock
should be limited to 17 Mbps, which allows it to read an ADC
result in less than 1 μs. When a higher sampling rate is desired,
use of one of the parallel interface modes is recommended.
DVDD
SER/PAR
EXT/INT
RD
INVSCLK
Figure 33. Interfacing the AD7655 to SPI Interface
AD7655*
*ADDITIONAL PINS OMITTED FOR CLARITY
SDOUT
CNVST
BUSY
SCLK
CS
SPIxSEL (PFx)
MISOx
SCKx
PFx
PFx or TFSx
ADSP-219x*

Related parts for AD7655