AD7982 Analog Devices, AD7982 Datasheet - Page 20

• Manufacturer Part Number: AD7982
• Manufacturer: Analog Devices

Specifications of AD7982

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP

AD7982
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7982 is connected
to an SPI-compatible digital host with an interrupt input and
when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This independence is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 35, and the
corresponding timing is given in Figure 36.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
ACQUISITION
SDO
CNV
SCK
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
Figure 36. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Figure 35. CS Mode, 4-Wire with Busy Indicator Connection Diagram
t
EN
SDI
AD7982
CNV
SCK
1
Rev. A | Page 20 of 24
t
t
HSDO
DSDO
SDO
D17
2
VIO
47kΩ
t
CYC
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7982
then enters the acquisition phase and powers down. The data
bits are then clocked out, MSB first, by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 19
SDI going high (whichever occurs first), SDO returns to high
impedance.
D16
3
ACQUISITION
CONVERT
DATA IN
CLK
CS1
IRQ
DIGITAL HOST
t
ACQ
t
SCKL
t
SCKH
17
t
SCK
18
D1
19
D0
t
DIS
th
SCK falling edge or