AD7982 Analog Devices, AD7982 Datasheet - Page 18

• Manufacturer Part Number: AD7982
• Manufacturer: Analog Devices

Specifications of AD7982

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP

AD7982
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7982 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 31, and the
corresponding timing is given in Figure 32.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
ACQUISITION
SDI = 1
CNV
SCK
SDO
t
CNVH
CONVERSION
Figure 32. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Figure 31. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
t
CONV
VIO
SDI
AD7982
CNV
SCK
1
Rev. A | Page 18 of 24
t
HSDO
SDO
D17
2
t
CYC
VIO
ACQUISITION
47kΩ
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7982 then
enters the acquisition phase and powers down. The data bits are
then clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 19
or when CNV goes high (whichever occurs first), SDO returns
to high impedance.
If multiple AD7982s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
D16
t
3
ACQ
t
DSDO
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
t
SCKL
t
SCKH
17
t
SCK
18
D1
19
D0
t
DIS
th
SCK falling edge