AD7195 Analog Devices, AD7195 Datasheet - Page 29

• Manufacturer Part Number: AD7195
• Description: 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation
• Manufacturer: Analog Devices

Specifications of AD7195

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/ RDY lines are used to
communicate with the AD7195. The end of the conversion can
be monitored using the RDY bit or pin. This scheme is suitable
for interfacing to microcontrollers. If CS is required as a decoding
signal, it can be generated from a port pin. For microcontroller
interfaces, it is recommended that SCLK idle high between data
transfers.
The AD7195 can be operated with CS used as a frame synchro-
nization signal. This scheme is useful for DSP interfaces. In this
case, the first bit (MSB) is effectively clocked out by CS because
CS normally occurs after the falling edge of SCLK in DSPs. The
SCLK can continue to run between data transfers, provided the
timing numbers are obeyed.
The serial interface can be reset by writing a series of 1s to the
DIN input. If a Logic 1 is written to the AD7195 DIN line for
at least 40 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface gets lost due to a software error or some glitch in the
system. Reset returns the interface to the state in which it expects
a write to the communications register. This operation resets the
contents of all registers to their power-on values. Following a
reset, the user should allow a period of 500 μs before addressing
the serial interface.
The AD7195 can be configured to continuously convert or to
perform a single conversion (see Figure 21 through Figure 23).
DOUT/RDY
SCLK
DIN
CS
0x08
0x280060
Figure 21. Single Conversion
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Single Conversion Mode
In single conversion mode, the AD7195 is placed in power-
down mode after conversions. When a single conversion is
initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively,
in the mode register, the AD7195 powers up, performs a single
conversion, and then returns to power-down mode. The on-
chip oscillator requires 1 ms, approximately, to power up.
DOUT/ RDY goes low to indicate the completion of a conver-
sion. When the data-word has been read from the data register,
DOUT/ RDY goes high. If CS is low, DOUT/ RDY remains high
until another conversion is initiated and completed. The data
register can be read several times, if required, even when
DOUT/ RDY has gone high.
If several channels are enabled, the ADC sequences through the
enabled channels and performs a conversion on each channel.
When a conversion is started, DOUT/ RDY goes high and
remains high until a valid conversion is available. As soon as
the conversion is available, DOUT/ RDY goes low. The ADC
then selects the next channel and begins a conversion. The user
can read the present conversion while the next conversion is
being performed. As soon as the next conversion is complete,
the data register is updated; therefore, the user has a limited
period in which to read the conversion. When the ADC has
performed a single conversion on each of the selected channels,
it returns to power-down mode.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The four LSBs of the status
register indicate the channel to which the conversion corresponds.
0x58
DATA
AD7195