AD7195 Analog Devices, AD7195 Datasheet - Page 18

• Manufacturer Part Number: AD7195
• Description: 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation
• Manufacturer: Analog Devices

Specifications of AD7195

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7195
COMMUNICATIONS REGISTER
(RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register.
All communications to the part must start with a write
operation to the communications register. The data written
to the communications register determines whether the next
operation is a read or a write operation and in which register
this operation takes place. For read or write operations, when
the subsequent read or write operation to the selected register
is complete, the interface returns to where it expects a write
operation to the communications register. This is the default
CR7
WEN(0)
Table 19. Communications Register Bit Designations
Bit Location
CR7
CR6
CR5 to CR3
CR2
CR1 to CR0
Table 20. Register Selection
RS2
0
0
0
0
0
1
1
1
1
RS1
0
0
0
1
1
0
0
1
1
CR6
R/W(0)
Bit Name
WEN
R/W
RS2 to RS0
CREAD
0
0
0
1
0
1
0
1
0
1
RS0
Register
Communications register during a write operation
Status register during a read operation
Mode register
Configuration register
Data register/data register plus status information
ID register
GPOCON register
Offset register
Full-scale register
Description
Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is
the first bit written, the part does not clock on to subsequent bits in the register; rather, it stays at this bit
location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to
the communications register. Idling the DIN pin high between data transfers minimizes the effects of
spurious SCLK pulses on the serial interface.
A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position
indicates that the next operation is a read from the designated register.
Register address bits. These address bits are used to select which registers of the ADC are selected during
the serial interface communication (see Table 20).
Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial
interface is configured so that the data register can be continuously read; that is, the contents of the data
register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin
goes low to indicate that a conversion is complete. The communications register does not have to be
written to for subsequent data reads. To enable continuous read, the Instruction 01011100 must be written
to the communications register. To disable continuous read, the Instruction 01011000 must be written to
the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors
activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset
occurs if 40 consecutive 1s are seen on DIN. Therefore, hold DIN low until an instruction is written to the
device.
These bits must be programmed to Logic 0 for correct operation.
CR5
RS2(0)
CR4
RS1(0)
Rev. 0 | Page 18 of 44
CR3
RS0(0)
state of the interface and, on power-up or after a reset, the
ADC is in this default state waiting for a write operation to
the communications register. In situations where the interface
sequence is lost, a write operation of at least 40 serial clock
cycles with DIN high returns the ADC to this default state by
resetting the entire part. Table 19 outlines the bit designations
for the communications register. CR0 through CR7 indicate the
bit location, CR denoting that the bits are in the communications
register. CR7 denotes the first bit of the data stream. The
number in parentheses indicates the power-on/reset default
status of that bit.
CR2
CREAD(0)
CR1
0
Register Size
8 bits
8 bits
24 bits
24 bits
24 bits/32 bits
8 bits
8 bits
24 bits
24 bits
CR0
0