SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 464

• Manufacturer Part Number: SAM3N2A
• Manufacturer: Atmel Corporation

Specifications of SAM3N2A

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.2
28.3
464
464
Embedded Characteristics
List of Abbreviations
SAM3N
SAM3N
Note:
Table 28-2.
Abbreviation
TWI
A
NA
P
S
Sr
SADR
ADR
R
W
• Two TWIs
• Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
• One, Two or Three Bytes for Slave Address
• Sequential Read-write Operations
• Master, Multi-master and Slave Mode Operation
• Bit Rate: Up to 400 Kbits
• General Call Supported in Slave mode
• SMBUS Quick Command Supported in Master Mode
• Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data
• Connection to DMA Controller (DMAC) Channel Capabilities Optimizes Data Transfers in
Transfers in Master Mode Only
Master Mode Only
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
See
Table 28-1
Abbreviations
for details on compatibility with I²C Standard.
Description
Two-wire Interface
Acknowledge
Non Acknowledge
Stop
Start
Repeated Start
Slave Address
Any address except SADR
Read
Write
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
(Note:)