SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 291

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SAM3N2A

Manufacturer Part Number
SAM3N2A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N2A

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
19. Fast Flash Programming Interface (FFPI)
19.1
19.2
19.2.1
11011A–ATARM–04-Oct-10
Description
Parallel Fast Flash Programming
Device Configuration
The Fast Flash Programming Interface provides parallel high-volume programming using a stan-
dard gang programmer. The parallel interface is fully handshaked and the device is considered
to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all
the embedded Flash functionalities.
Although the Fast Flash Programming Mode is a dedicated mode for high volume programming,
this mode is not designed for in-situ programming.
In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins
is significant. The rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in
bypass mode. Other pins must be left unconnected.
Figure 19-1. SAM3NxA (48 bits) Parallel Programming Interface
Figure 19-2. SAM3NxB/C (64/100 pins) Parallel Programming Interface
MODE[3:0]
MODE[3:0]
DATA[15:0]
0 - 50MHz
0 - 50MHz
DATA[7:0]
NVALID
NVALID
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
NCMD
NCMD
GND
GND
NOE
NOE
RDY
RDY
PGMD[15:0]
TST
PGMEN0
PGMEN1
PGMEN2
PGMNCMD
PGMRDY
PGMNOE
PGMNVALID
PGMM[3:0]
XIN
TST
PGMEN0
PGMEN1
PGMEN2
PGMNCMD
PGMRDY
PGMNOE
PGMNVALID
PGMM[3:0]
PGMD[7:0]
XIN
VDDCORE
VDDIO
VDDPLL
GND
VDDCORE
VDDIO
VDDPLL
GND
SAM3N
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