ATxmega64A4U Atmel Corporation, ATxmega64A4U Datasheet - Page 138

• Manufacturer Part Number: ATxmega64A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.8.3
12.9
8331A–AVR–07/11
Address
+0x00
+0x01
+0x02
Register Summary
CTRL – PMIC Control Register
Name
STATUS
INTPRI
CTRL
to change the priority queue. This register is not reinitialized to its initial value if round-robing
scheduling is disabled, and so if default static priority is needed, the register must be written to
zero.
• Bit 7 – RREN: Round-robin Scheduling Enable
When the RREN bit is set, the round-robin scheduling scheme is enabled for low-level interrupts.
When this bit is cleared, the priority is static according to interrupt vector address, where the low-
est address has the highest priority.
• Bit 6 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the applica-
tion section in flash. When this bit is set (one), the interrupt vectors are moved to the beginning
of the boot section of the flash. Refer to the device datasheet for the absolute address.
This bit is protected by the configuration change protection mechanism. Refer to
Change Protection” on page 12
• Bit 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 – HILVLEN: High-level Interrupt Enable
When this bit is set, all high-level interrupts are enabled. If this bit is cleared, high-level interrupt
requests will be ignored.
• Bit 1 – MEDLVLEN: Medium-level Interrupt Enable
When this bit is set, all medium-level interrupts are enabled. If this bit is cleared, medium-level
interrupt requests will be ignored.
• Bit 0 – LOLVLEN: Low-level Interrupt Enable
When this bit is set, all low-level interrupts are enabled. If this bit is cleared, low-level interrupt
requests will be ignored.
Note:
NMIEX
Bit 7
Bit
+0x02
Read/Write
Initial Value
RREN
1. Ignoring interrupts will be effective one cycle after the bit is cleared.
Bit 6
IVSEL
RREN
–
R/W
7
0
IVSEL
Bit 5
R/W
6
0
–
–
for details.
R
5
–
0
Bit 4
–
–
INTPRI[7:0]
R
4
–
0
Bit 3
–
–
(1)
(1)
Atmel AVR XMEGA AU
R
3
–
0
HILVLEX
HILVLEN
Bit 2
(1)
HILVLEN
R/W
2
0
MEDLVLEN
MEDLVLEX
Bit 1
MEDLVLEN
R/W
1
0
LOLVLEN
LOLVLEX
Bit 0
LOLVLEN
R/W
0
0
”Configuration
Page
CTRL
137
137
138
138