AT90CAN64 Automotive Atmel Corporation, AT90CAN64 Automotive Datasheet - Page 197
AT90CAN64 Automotive
Manufacturer Part Number
AT90CAN64 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(431 pages)
2.AT90CAN128_AUTOMOTIVE.pdf
(16 pages)
3.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
Specifications of AT90CAN64 Automotive
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT90CAN128_AUTOMOTIVE PDF datasheet #2
- AT90CAN128_AUTOMOTIVE PDF datasheet #3
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17.11.8
7682C–AUTO–04/08
USART1 Control and Status Register C – UCSR1C
• Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, these bit must be written
to zero when UCSRnC is written.
• Bit 6 – UMSELn: USARTn Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 17-4.
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 17-5.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 17-6.
Bit
Read/Write
Initial Value
UPMn1
UMSELn
0
0
1
1
0
1
UMSELn Bit Settings
UPMn Bits Settings
USBSn Bit Settings
USBSn
R
7
–
0
0
1
UMSEL1
R/W
6
0
UPMn0
Mode
Asynchronous Operation
Synchronous Operation
UPM11
0
1
0
1
R/W
5
0
UPM10
Stop Bit(s)
1-bit
2-bit
R/W
4
0
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
USBS1
R/W
3
0
UCSZ11
R/W
2
1
AT90CAN32/64/128
UCSZ10
R/W
1
1
UCPO1L
R/W
0
0
UCSR1C
197
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