AT89S4051 Atmel Corporation, AT89S4051 Datasheet - Page 5

• Manufacturer Part Number: AT89S4051
• Manufacturer: Atmel Corporation

Specifications of AT89S4051

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 15
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 2
• Isp: SPI

6. X2 Mode Description
7. Special Function Registers
3390E–MICRO–6/08
The clock for the entire circuit and peripherals is normally divided by 2 before being used by the
CPU core and peripherals. This allows any cyclic ratio (duty cycle) to be accepted on XTAL1
input. In X2 mode this divider is bypassed.
Figure 6-1.
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
XTAL1
7-1.
F
XTAL
Clock Generation Block Diagram
÷ 2
X2 Mode
(XTAL1)/2
Figure 6-1
shows the clock generation block diagram.
F
OSC
AT89S2051/S4051
State Machine: 6 Clock Cycles
CPU Control
5