AT89S4051 Atmel Corporation, AT89S4051 Datasheet - Page 11

• Manufacturer Part Number: AT89S4051
• Manufacturer: Atmel Corporation

Specifications of AT89S4051

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 15
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 2
• Isp: SPI

12.4
Table 12-1.
3390E–MICRO–6/08
Symbol
SMOD1
SMOD0
PWMEN
POF
GF1, GF0
PD
IDL
PCON = 87H
Not Bit Addressable
Bit
Reset Recovery from Power-down
Function
Double Baud Rate bit. Doubles the baud rate of the UART in modes 1, 2, or 3.
Frame Error Select. When SMOD0 = 0, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
Pulse Width Modulation Enable. When PWMEN = 1, Timer 0 and Timer 1 are configured as an 8-bit PWM counter with
8-bit auto-reload prescaler. The PWM outputs on T1 (P3.5).
Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST or BOD (i.e. warm resets).
General-purpose Flags
Power Down bit. Setting this bit activates power down operation.
Idle Mode bit. Setting this bit activates idle mode operation
PCON
SMOD1
7
– Power Control Register
Wakeup from Power-down through an external reset is similar to the interrupt with PWDEX = 0.
At the rising edge of RST, Power-down is exited, the is restarted, and an internal timer begins
counting. The internal clock will not be allowed to propagate to the CPU until after the timer has
counted for nominally 2 ms. The RST pin must be held high for longer than the timeout period to
ensure that the device is reset properly. The device will begin executing once RST is brought
low.
It should be noted that when idle is terminated by a hardware reset, the device normally
resumes program execution, from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.
P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pull-
ups are used.
.
SMOD0
6
PWMEN
5
POF
4
GF1
3
GF0
2
AT89S2051/S4051
Reset Value = 000X 0000B
PD
1
IDL
0
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