AT89S4051 Atmel Corporation, AT89S4051 Datasheet - Page 10

• Manufacturer Part Number: AT89S4051
• Manufacturer: Atmel Corporation

Specifications of AT89S4051

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 24 MHz
• Cpu: 8051-12C
• Max I/o Pins: 15
• Uart: 1
• Sram (kbytes): 0.25
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 2
• Isp: SPI

12. Power Saving Modes
12.1
12.2
12.3
10
Idle Mode
Power-down Mode
Interrupt Recovery from Power-down
AT89S2051/S4051
The AT89S2051/S4051 supports two power-reducing modes: Idle and Power-down. These
modes are accessed through the PCON register.
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logical states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
CPU when an interrupt is generated. Timer 0, Timer 1, and the UART will continue to function
during Idle mode. The analog comparator is disabled during Idle. Any enabled interrupt source
or reset may terminate Idle mode. When exiting Idle mode with an interrupt, the interrupt will
immediately be serviced, and following RETI, the next instruction to be executed will be the one
following the instruction that put the device into Idle.
P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pull-
ups are used.
Setting the PD bit in PCON enters Power-down mode. Power-down mode stops the and powers
down the Flash memory in order to minimize power consumption. Only the power-on circuitry
will continue to draw power during Power-down. During Power-down the power supply voltage
may be reduced to the RAM keep-alive voltage. The RAM contents will be retained; however,
the SFR contents are not guaranteed once V
by external reset, power-on reset, or certain interrupts.
The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 µs
until after one of the following conditions has occurred: Start of code execution (after any type of
reset), or Exit from power-down mode.
Two external interrupts may be configured to terminate Power-down mode. External interrupts
INT0 (P3.2) and INT1 (P3.3) may be used to exit Power-down. To wake up by external interrupt
INT0 or INT1, the interrupt must be enabled and configured for level-sensitive operation.
When terminating Power-down by an interrupt, two different wake up modes are available.
When PWDEX in CLKREG.2 is zero, the wake up period is internally timed. At the falling edge
on the interrupt pin, Power-down is exited, the is restarted, and an internal timer begins count-
ing. The internal clock will not be allowed to propagate and the CPU will not resume execution
until after the timer has counted for nominally 2 ms. After the timeout period the interrupt service
routine will begin. To prevent the interrupt from re-triggering, the ISR should disable the interrupt
before returning. The interrupt pin should be held low until the device has timed out and begun
executing.
When PWDEX = 1 the wakeup period is controlled externally by the interrupt. Again, at the fall-
ing edge on the interrupt pin, Power-down is exited and the is restarted. However, the internal
clock will not propagate and CPU will not resume execution until the rising edge of the interrupt
pin. After the rising edge on the pin, the interrupt service routine will begin. The interrupt should
be held low long enough for the to stabilize.
CC
has been reduced. Power-down may be exited
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