PM8316-PI PMC-Sierra Inc, PM8316-PI Datasheet
PM8316-PI
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PM8316-PI Summary of contents
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... HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 PROPRIETARY AND CONFIDENTIAL PMC-Sierra, Inc. ISSUE 4 PM8316 TEMUX-84 MULTIPLEXER DATASHEET PRELIMINARY ISSUE 4: MAY 2001 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... PIN DESCRIPTION................................................................................ 34 9 FUNCTIONAL DESCRIPTION............................................................... 72 9.1 TRANSPARENT VIRTUAL TRIBUTARIES.................................. 72 9.2 THE TRIBUTARY INDEXING ...................................................... 73 9.3 T1 FRAMING............................................................................... 75 9.4 E1 FRAMING .............................................................................. 78 9.5 T1/E1 PERFORMANCE MONITORING...................................... 84 9.6 T1/E1 HDLC RECEIVER............................................................. 85 9.7 T1/E1 ELASTIC STORE (ELST) ................................................. 86 9.8 T1/E1 SIGNALING EXTRACTION .............................................. 86 9.9 T1/E1 RECEIVE PER-CHANNEL CONTROL ............................. 87 PROPRIETARY AND CONFIDENTIAL ISSUE 4 i PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... E3 FRAMER.............................................................................. 107 9.26 E3 TRANSMITTER ................................................................... 109 9.27 E3 TRAIL TRACE BUFFER........................................................ 111 9.28 TRIBUTARY PAYLOAD PROCESSOR (VTPP) .........................112 9.29 RECEIVE TRIBUTARY PATH OVERHEAD PROCESSOR (RTOP) .......................................................................................114 9.30 RECEIVE TRIBUTARY TRACE BUFFER (RTTB)......................116 PROPRIETARY AND CONFIDENTIAL ISSUE 4 ii PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... MICROPROCESSOR INTERFACE .......................................... 135 10 NORMAL MODE REGISTER DESCRIPTION ..................................... 161 11 TEST FEATURES DESCRIPTION ...................................................... 162 11.1 JTAG TEST PORT .................................................................... 165 12 OPERATION ........................................................................................ 172 12.1 TRIBUTARY INDEXING ............................................................ 172 12.2 CLOCK AND FRAME SYNCHRONIZATION CONSTRAINTS .. 174 PROPRIETARY AND CONFIDENTIAL ISSUE 4 iii PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... DS3 AND E3 SYSTEM SIDE INTERFACE TIMING .................. 245 13.3 TELECOM DROP BUS INTERFACE TIMING........................... 249 13.4 TELECOM ADD BUS INTERFACE TIMING.............................. 252 13.5 SONET/SDH SERIAL ALARM PORT TIMING .......................... 255 13.6 SBI DROP BUS INTERFACE TIMING ...................................... 256 PROPRIETARY AND CONFIDENTIAL ISSUE 4 iv PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE 7 - DS3/E3 FRAMER ONLY MODE BLOCK DIAGRAM ................... 27 FIGURE 8 - PIN DIAGRAM ............................................................................. 33 FIGURE 9 - CRC MULTIFRAME ALIGNMENT ALGORITHM ......................... 81 FIGURE 10- JITTER TOLERANCE T1 MODES .............................................. 92 FIGURE 11 - JITTER TOLERANCE E1 MODES .............................................. 93 FIGURE 12- JITTER TRANSFER T1 MODES ................................................. 94 PROPRIETARY AND CONFIDENTIAL ISSUE 4 v PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE 32- BOUNDARY SCAN ARCHITECTURE....................................... 233 FIGURE 33- TAP CONTROLLER FINITE STATE MACHINE......................... 235 FIGURE 34- INPUT OBSERVATION CELL (IN_CELL).................................. 238 FIGURE 35- OUTPUT CELL (OUT_CELL) .................................................... 239 FIGURE 36- BIDIRECTIONAL CELL (IO_CELL) ........................................... 239 PROPRIETARY AND CONFIDENTIAL ISSUE 4 vi PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE 54- FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM ......... 248 FIGURE 55- FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM WITH TGAPCLK .......................................................................... 248 FIGURE 56- FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM........ 249 PROPRIETARY AND CONFIDENTIAL ISSUE 4 vii PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... FIGURE 74- SBI ADD BUS TIMING............................................................... 280 FIGURE 75- SBI DROP BUS TIMING............................................................ 282 FIGURE 76- SBI DROP BUS COLLISION AVOIDANCE TIMING .................. 282 FIGURE 77- EGRESS FLEXIBLE BANDWIDTH PORT TIMING ................... 283 PROPRIETARY AND CONFIDENTIAL ISSUE 4 viii PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... TABLE 9 - REGISTER MEMORY MAP....................................................... 135 TABLE 10 - INSTRUCTION REGISTER ....................................................... 165 TABLE 11 - IDENTIFICATION REGISTER ................................................... 165 TABLE 12 - BOUNDARY SCAN REGISTER ................................................ 166 TABLE 13 - INDEXING FOR 1.544 MBIT/S TRIBUTARIES.......................... 173 PROPRIETARY AND CONFIDENTIAL ISSUE 4 ix PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... TABLE CHANNEL ASSOCIATED SIGNALING BITS........................ 215 TABLE FRAMING FORMAT ............................................................. 217 TABLE CHANNEL ASSOCIATED SIGNALING BITS ....................... 218 TABLE 34 - DS3 FRAMING FORMAT .......................................................... 219 TABLE 35 - DS3 BLOCK FORMAT............................................................... 220 PROPRIETARY AND CONFIDENTIAL ISSUE 4 x PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... TABLE 54 - SBI ADD BUS TIMING – 19.44 MHZ (FIGURE 74) ................... 278 TABLE 55 - SBI ADD BUS TIMING – 77.76 MHZ (FIGURE 74) ................... 279 TABLE 56 - SBI DROP BUS TIMING - 19.44 MHZ (FIGURE 72 FIGURE 75 AND ) ........................................................................................... 280 PROPRIETARY AND CONFIDENTIAL ISSUE 4 xi PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... TABLE 63 - TRANSMIT LINE INTERFACE TIMING (FIGURE 82) ............... 289 TABLE 64 - REMOTE SERIAL ALARM PORT TIMING ................................ 290 TABLE 65 - JTAG PORT INTERFACE.......................................................... 291 TABLE 66 - ORDERING INFORMATION...................................................... 293 TABLE 67 - THERMAL INFORMATION – THETA JA VS. AIRFLOW ............ 293 PROPRIETARY AND CONFIDENTIAL ISSUE 4 xii PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... VT1.5 virtual tributaries or TU-11 tributary units, providing a transmultiplexing function between DS3 and SONET/SDH. • streams mapped as bit asynchronous TU-12 tributary units into three STM-1/VC3 or TUG3 from a STM-1/VC4. PROPRIETARY AND CONFIDENTIAL ISSUE 4 1 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Supports insertion and extraction of arbitrary rate (eg. fractional DS3) data streams to and from the SBI bus interface. • Provides jitter attenuation in the receive and transmit directions. PROPRIETARY AND CONFIDENTIAL ISSUE 4 2 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... CRC-6 calculation for Japanese applications. • Provides Red, Yellow, and AIS alarm integration. • Supports RAI-CI and AIS-CI alarm detection and generation. PROPRIETARY AND CONFIDENTIAL ISSUE operation. 3 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Frames in the presence of and detects the “Japanese Yellow” alarm. • Supports the alternate CRC-6 calculation for Japanese applications. • Provides external access for up to three de-jittered recovered T1 clocks. PROPRIETARY AND CONFIDENTIAL ISSUE 4 4 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX – ...
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... Line side interface is from the SONET/SDH Drop bus via the VT2 or TU-12 demapper. • System side interface is either H-MVIP or SBI bus. • Provides external access for up to three de-jittered recovered E1 clocks. PROPRIETARY AND CONFIDENTIAL ISSUE 4 5 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX – ...
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... Supports unframed mode and framing bit, CRC, or data link by-pass. • Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per channel basis. PROPRIETARY AND CONFIDENTIAL ISSUE 4 6 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX – ...
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... PM5362 TUPP-PLUS and PM5342 SPECTRA-155 at 19.44 MHz. • Seamlessly interfaces with a 77.76 MHz Drop bus. Interfaces to a 77.76 MHz Add bus with minimal external logic. PROPRIETARY AND CONFIDENTIAL ISSUE 4 7 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX – ...
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... Support in-band error reporting by updating the FEBE, RDI and auxiliary RDI bits in the V5 byte with the status of the incoming stream and remote alarm pins. PROPRIETARY AND CONFIDENTIAL ISSUE 4 8 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... STS-1 SPE into E1 streams via an optional elastic store. • Extracts bit asynchronous mapped TU-12 tributary units from an STM-1/VC4 TUG3 or STM-1/VC3 into streams via an optional elastic store. PROPRIETARY AND CONFIDENTIAL ISSUE 4 9 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... C-bit parity mode operation 16,383 C-bit parity error events per second, and 16,383 far end block error (FEBE) events per second. PROPRIETARY AND CONFIDENTIAL ISSUE 4 10 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate.Extracts ...
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... Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled and interrupt-driven operation. • Provides programmable pseudo-random test sequence generation ( bit length sequences conforming to ITU-T O.151 standards) or any PROPRIETARY AND CONFIDENTIAL ISSUE 4 11 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end receive failure (FERF). • Accumulates up to 255 DS2 M-bit or F-bit error events per second. PROPRIETARY AND CONFIDENTIAL ISSUE 4 12 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Frames to G.751 and G.832 E3 unchannelized data streams. • For G.832, terminates the Trail Trace and either the Network Requirement or the General Purpose data link. PROPRIETARY AND CONFIDENTIAL ISSUE 4 13 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... H-MVIP data interfaces. • Alarm status, T1 F-bit and inband signaling control is available using otherwise unused bit positions. • Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s. PROPRIETARY AND CONFIDENTIAL ISSUE 4 14 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Transmit timing is mastered either by the TEMUX- layer 2 device connecting to the SBI bus. Timing mastership is selectable on a per tributary basis, where a tributary is either an individual T1, E1 DS3. PROPRIETARY AND CONFIDENTIAL ISSUE 4 15 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... M23 Based M13 Multiplexer • C-Bit Parity Based M13 Multiplexer • Channelized and Unchannelized DS3 Frame Relay Interfaces • Optical Access Equipment • Digital Access Cross-Connect Systems PROPRIETARY AND CONFIDENTIAL ISSUE 4 16 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Bell Communications Research - Alarm Indication Signal Requirements and Objectives, TR-TSY-000191 Issue 1, May 1986 • Bell Communications Research - Wideband and Broadband Digital Cross- Connect Systems Generic Criteria, TR-NWT-000233, Issue 3, November 1993 PROPRIETARY AND CONFIDENTIAL ISSUE 4 17 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Functional Requirements for Synchronous Digital Hierarchy (SDH) equipment; Part 1-1: Generic processes and performance,” January, 1996. • ETSI, Generic Functional Requirements for Synchronous Digital Hierarchy (SDH) Equipment, Jan 1996 PROPRIETARY AND CONFIDENTIAL ISSUE 4 18 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... ITU-T - Recommendation I.431 - Primary Rate User-Network Interface – Layer 1 Specification, 1993. • ITU-T Recommendation O.151 – Error Performance Measuring Equipment Operating at the Primary Rate and Above, October 1992 PROPRIETARY AND CONFIDENTIAL ISSUE 4 19 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Nippon Telegraph and Telephone Corporation - Technical Reference for High- Speed Digital Leased Circuit Services, Third Edition, 1990. • GO-MVIP, Multi-Vendor Integration Protocol, MVIP-90, Release 1.1, 1994 • GO-MVIP, H-MVIP Standard, Release1.1a, 1997 PROPRIETARY AND CONFIDENTIAL ISSUE 4 20 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... ATM inverse multiplexing (IMA84) may all be supported on the same port with a common SBI bus as the enabling technology. PROPRIETARY AND CONFIDENTIAL ISSUE 4 SBI FREEDM 84A672 TEMUX AAL1gator32 84 21 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX APPI Utopia Packet/Cell Interworking Function IMA ...
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... Fractional DS3 Application DS3 LIU 44.736 MHz PROPRIETARY AND CONFIDENTIAL ISSUE 4 APPI SBI FREEDM 84A672 FREEDM 84A672 FREEDM 84A672 FREEDM 84A672 FPGA TEM UX-84 FPGA 22 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX UTOPIA Packet/Cell Interworking Function SBI Bus ...
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... Bandwidth Port responds by asserting EFWBEN coincident with EFWBDAT presenting valid data. The SBI Add bus participates by modulating its SAJUST_REQ output to match the SBI data rate to that required to keep internal FIFOs centered. PROPRIETARY AND CONFIDENTIAL ISSUE 4 23 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... INSBI (byte) TTMP T1/E1 T1/E1 JAT84 TRAN84 (bit) T1/E1 RTDM T1/E1 FRMR84 (bit) JAT84 EXSBI (byte M13 SIPO 24 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Egress Flexible B/W Port Egress H-M VIP H-MVIP T1/E1 EXSBI ELST84 SBI 155 T1/E1 INSBI ELST84 T1/E1 SIGX84 Ingress H-M VIP ...
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... M 13 TRAN DS3 M 13 LIUs FRM R PROPRIETARY AND CONFIDENTIAL ISSUE 4 T1/E1 T1/E1 PISO TRAN84 JAT84 T1/E1 T1/E1 FRM R84 JAT84 SIPO 25 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Egress H-M VIP H-M VIP T1/E1 ELST84 T1/E1 Ingress ELST84 H-M VIP T1/E1 H-M VIP SIGX84 ...
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... M13 VTPP Telecom Bus M13 M13 VTPP PROPRIETARY AND CONFIDENTIAL ISSUE 4 INSBI TTOP TRAP TTMP (bit) M13 RTDM M 13 RTOP/ (bit) RTTB EXSBI 26 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX T1/E1 EXSBI JAT84 T1/E1 FRMR84 T1/E1 INSBI JAT84 SBI 155 ...
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... HD LC TRAN B3ZS/ DS3/E3 HDB 3 Transm it Fram er FRM R B3ZS/ DS3/ eceive Fram er PMO Perf. M onitor 3X 27 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX TFP O/TMFPO /TG APC LK TFP I APCLK/RSCLK RD ATO RFPO /R MFPO RO VRHD ...
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... DATASHEET PMC-1991437 6 DESCRIPTION The PM8316 High Density T1/E1 Framer with Integrated VT/TU Mappers and M13 Multiplexers (TEMUX-84 feature-rich device for use in any applications requiring high density link termination over T1 and E1 (G.747) channelized DS3 or T1 and E1 channelized SONET/SDH facilities. The TEMUX-84 supports asynchronous multiplexing and demultiplexing of 84 DS1s or 63 E1s into three DS3 signals as specified by ANSI T1 ...
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... Framing can be optionally disabled. Transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported. PRBS generation or detection is supported on a framed and unframed E1 basis. PROPRIETARY AND CONFIDENTIAL ISSUE 4 29 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... Transfer of count values to holding registers is initiated through the microprocessor interface. PROPRIETARY AND CONFIDENTIAL ISSUE 4 30 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate -3 ...
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... Each of the seven 6312 kbit/s multiplexers per DS3 may be independently configured to multiplex and demultiplex four 1544 kbit/s DS1s or three 2048 kbit/s according to ITU-T Rec. G.747 into and out of a DS2 formatted PROPRIETARY AND CONFIDENTIAL ISSUE 4 31 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... The TEMUX-84 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface. PROPRIETARY AND CONFIDENTIAL ISSUE 4 32 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Bottom View 33 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX VSS VSS VSS VSS VSS VSS ...
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... RFALL bit in the DS3/E3 Master Receive Line Options register. Transmit Clock (TCLK[3:1]). TCLK[3:1] provide V1 timing for circuitry downstream of the DS3 and E3 W3 transmitters of the TEMUX-84. TCLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clocks. 34 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... DS3/E3 Master Transmit Line Options register is set. T4 Transmit input clock (TICLK[3:1]). TICLK[3:1] V4 provides the transmit direction timing for the three Y2 DS3s or E3s. TICLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clocks. 35 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... RGAPCLK or RSCLK, depending on the value of the RSCLKR bit in the DS3 and E3 Master Unchannelized Interface Options register. By default, RDATO[3:1] will be updated on the falling edge of the associated RGAPCLK[3:1] or RSCLK[3:1]. 36 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... RDATO[3:1] corresponds to an overhead bit position. ROVRHD[3:1] is updated on the either the falling or rising edge of the associated RSCLK depending on the setting of the RSCLKR bit in the DS3 and E3 Master Unchannelized Interface Options register. 37 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... TGAPCLK[3:1] are held high during the overhead bit positions. This clock is useful for interfacing to devices which source payload data only. TGAPCLK[3:1] are used to sample the associated TDATI[3:1] inputs. 38 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... TFPI/TMFPI[3:1] are sampled on the rising edge of the associated TICLK. TDATI[3:1] can be configured to be sampled on the falling edge of the associated TICLK by setting the TDATIFALL bit the DS3 and E3 Master Unchannelized Interface Options register. 39 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... The H-MVIP interfaces are enabled via the SYSOPT[1:0] bits in the Global Configuration registers. If the TEMUX-84 is not configured for H-MVIP operation, this clock may be tied high or low. 40 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... SYSOPT[1:0] bits in the Global Configuration register. If the TEMUX-84 is not configured for H-MVIP operation, this frame pulse may be tied high or low. The CMVFPB frame pulse occurs at multiples of 125us and is sampled on the falling edge of CMVFPC. 41 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... T1 and E1 links may be mixed on a TUG-3/DS3 B8 granularity. Each of MVID[1:7], MVID[8:14] and A8 MVID[15:21] carries 28 T1s or 21 E1s independent of D7 the other two groups of seven. For E1 mode, MVID[7], C9 MVID[14] and MVID[21] are unused PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The updating edge of CMV8MCLK is selected via the CMVIDE bit in the Master H-MVIP Interface Configuration register. 43 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... A15 granularity. Each of MVED[1:7], MVED[8:14] and B15 MVED[15:21] carries 28 T1s or 21 E1s independent of A16 the other two groups of seven. For E1 mode, C15 MVED[7], MVED[14] and MVED[21] are unused. B16 A17 44 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... CMV8MCLK as fixed by the common H-MVIP frame pulse clock, CMVFPC. The sampling edge of CMV8MCLK is selected via the CMVEDE bit in the Master H-MVIP Interface Configuration register. 45 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... IFBWDAT input. The IFBWEN[3:1] inputs are constrained such that the maximum data rate of each of IFBWDAT[3:1] is less than 49.72 Mbit/s. IFBWEN[3:1] are sampled on the rising edge of the associated IFBWCLK input. 46 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... In applications where the source data is fixed permissible to hold EFBWDREQ[3:1] high, in which case EFBWEN identifies valid bytes. EFBWDREQ[3:1] are sampled on the rising edge of the associated EFBWCLK input. 47 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... T1 framers framers. Recovered Clock 3 (RECVCLK3). This clock output is a recovered and de-jittered clock from any one of the 84 T1 framers framers. 48 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... This clock may be held low if the Telecom Bus interface is unused. This clock is nominally a 19.44 MHz +/-50ppm or 77.76 MHz +/-50ppm clock with a 50% duty cycle. This clock must be phase locked to SREFCLK and can be external connected to SREFCLK. 49 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... When L77 high, LAC1J1V1 is only valid (i.e. identifies the first C1, J1 and V1 of the concatenated STM-4 data stream) if the LSTM[1:0] bits in the Master Bus Configuration register (0x0006) are set to “00”. LAC1J1V1 is updated on the rising edge of LREFCLK. 50 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... LATPL will be low during transport overhead, path overhead, V1 bytes and V2 bytes. To indicate pointer adjustments, LATPL will be asserted appropriately during the V3 byte and following byte for the tributary. LAOE/LATPL is updated on the rising edge of LREFCLK. 51 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... LAOE bit in the TTMP Tributary Control registers. As options, LADP can be driven during transport overhead, for all bytes of an STM-1 when configured for 77.76MHz operation or all the time. LADP is updated on the rising edge of LREFCLK. 52 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... SONET/SDH receive payload data in AB5 byte serial format. LDDATA[7] is the most significant Y3 bit, corresponding to bit 1 of each serial word, the bit Y6 transmitted first. AA5 LDDATA[7:0] is sampled on the rising edge of AB4 LREFCLK. AB3 53 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... LDPL is set high during the H3 byte to indicate a negative pointer justification and low during the byte following H3 to indicate a positive pointer justification event. LDPL is sampled on the rising edge of LREFCLK. 54 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
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... LDDATA[7:0] that are in AIS state. When this signal is available, the internal pointer processor can be bypassed. LDAIS is invalid when LDTPL is low. LDAIS is only respected for asynchronously mapped tributaries. LDAIS is sampled on the rising edge of LREFCLK. 55 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 69
... The status carried on RADEAST is software selectable to be reported by the RDI, RFI and REI alarms and is selectable to be associated with any tributary on the outgoing data stream LADATA[7:0]. RADEAST is sampled on the rising edge of RADEASTCK. 56 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 70
... The status carried on RADWEST is software selectable to be reported by the RDI, RFI and REI alarms and is selectable to be associated with any tributary on the outgoing data stream LADATA[7:0]. RADWESTFP is sampled on the rising edge of RADWESTCK. 57 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 71
... When the SYSOPT register bits are binary 01 (H-MVIP interface), SREFCLK is required to be 19.44 MHz. When passing transparent virtual tributaries between the telecom bus and the SBI bus, SREFCLK must be the same as LREFCLK. 58 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 72
... SDC1FP pulses occur. The system frame pulse is a single SREFCLK cycle long and is updated on the rising edge of SREFCLK. This signal must be held low if the SBI bus is not being used. 59 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 73
... SADATA[7:0], SAPL and SAV5. The TEMUX-84 monitors the add bus parity during all cycles when S77 is low and during the entire selected STM-1 when S77 is high. SADP is sampled on the rising edge of SREFCLK. 60 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 74
... All timing adjustments indicated by this signal must be accompanied by appropriate adjustments in the SAPL signal. The TEMUX-84 only monitors the add bus payload indicator signal during the tributary timeslots assigned to this device. SAV5 is sampled on the rising edge of SREFCLK. 61 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 75
... When operating in 19.44 MHz mode (i.e. S77 low), SAJUST_REQ is aligned by the SAC1FP input. When operating in 77.76 MHz mode (i.e. S77 high), SAJUST_REQ’s alignment is relative to the SDC1FP signal. SAJUST_REQ is updated on the rising edge of SREFCLK. 62 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 76
... Therefore, SDPL may be high or low arbitrarily during any SREFCLK cycle. The TEMUX-84 only drives the payload active signal during the tributary timeslots assigned to this device. SDPL is updated on the rising edge of SREFCLK. 63 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 77
... S77 is low). A collision is detected when either of SBIDET[1:0] signals are active concurrently with this device driving SBIACT. When collisions occur the SBI drivers are disabled and an interrupt is generated to signal the collision. 64 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 78
... WRB edge while CSB is low. U22 Bidirectional Data Bus (D[7:0]). This bus provides T20 TEMUX-84 register read and write accesses. V19 U21 U20 W22 Y22 Y21 65 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 79
... Test Data Input (TDI). This signal carries test data into the TEMUX-84 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. 66 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 80
... Note that if not used, TRSTB must be connected to the RSTB input. Power (VDD3.3[19:1]). The VDD3.3[19:1] pins should A22 be connected to a well decoupled +3.3V DC power AB17 supply. D11 D16 D4 E1 F20 L1 L19 R21 R4 V2 W16 W4 W8 Y18 Y20 Y5 67 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 81
... PROPRIETARY AND CONFIDENTIAL ISSUE 4 Pin Function No. Power (VDD1.8[19:1]). The VDD1.8[19:1] pins should D3 be connected to a well-decoupled +1.8V DC power J2 supply AB2 AB9 Y12 Y15 AB19 N4 V20 U19 N21 K21 C22 C18 A13 B7 68 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 82
... AA3 AA7 AB12 AB15 AB21 AB8 B4 C11 C17 C19 C3 D15 D19 D22 G19 G4 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K3 K9 L10 L11 L12 L13 L14 69 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 83
... N14 N9 P10 P11 P12 P13 P14 P9 T2 V21 V22 W21 Y11 Y14 Y17 A1 These balls have no internal connections. They may B2 be left floating or tied to a static logic level T19 70 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 84
... Power to the VDD3.3 pins should be applied before power to the VDD1.8 pins is applied. Similarly, power to the VDD1.8 pins should be removed before power to the VDD3.3 pins is removed. PROPRIETARY AND CONFIDENTIAL ISSUE 4 71 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 85
... V1-V5 is transferred without modification. If IVTPPBYP is logic 0, V1/V2 must contain a valid pointer. The V1/V2 will be modified in the process of mapping the TVT into the SBI Drop Bus, which by definition has a PROPRIETARY AND CONFIDENTIAL ISSUE 4 72 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 86
... Table 13 and Table 14 provide the equivalencies between the various multiplex and mapping formats. Alternately, the formats can be equated with the following formulae: 1.544Mbit/s SBI LINK # PROPRIETARY AND CONFIDENTIAL ISSUE 4 = 7*(TU11-1) + TUG2 = 4*(DS2-1)+DS1 = 4*(MVED index – 7*SPE - 1) + DS1 73 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 87
... SBI Bus Telecom Bus SPE, LINK TUG-3, TUG-2, 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 1,10 1,11 1,12 1,13 1,14 1,15 1,16 1,17 1,18 1,19 1,20 1,21 1,22 1,23 1,24 1,25 1,26 1,27 1,28 2,1 ... PROPRIETARY AND CONFIDENTIAL ISSUE 4 = 7*(TU12-1) + TUG2 = 3*(DS2-1)+E1 = 4*(MVED index – 7*SPE - M13 DS3, DS2, TU11 DS1 1,1,1 1,1,1 1,2,1 1,1,2 1,3,1 1,1,3 1,4,1 1,1,4 1,5,1 1,2,1 1,6,1 1,2,2 1,7,1 1,2,3 1,1,2 1,2,4 1,2,2 1,3,1 1,3,2 1,3,2 1,4,2 1,3,3 1,5,2 1,3,4 1,6,2 1,4,1 1,7,2 1,4,2 1,1,3 1,4,3 1,2,3 1,4,4 1,3,3 1,5,1 1,4,3 1,5,2 1,5,3 1,5,3 1,6,3 1,5,4 1,7,3 1,6,1 1,1,4 1,6,2 1,2,4 1,6,3 1,3,4 1,6,4 1,4,4 1,7,1 1,5,4 1,7,2 1,6,4 1,7,3 1,7,4 1,7,4 2,1,1 2,1,1 ... ... 74 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX H-MVIP port index, DS1 1,1 1,2 1,3 1,4 2,1 2,2 2,3 2,4 3,1 3,2 3,3 3,4 4,1 4,2 4,3 4,4 5,1 5,2 5,3 5,4 6,1 6,2 6,3 6,4 7,1 7,2 7,3 7,4 8,1 ... ...
Page 88
... When searching for frame each of the 193 (SF or SLC96) or each of the 772 (ESF) framing bit candidates is simultaneously examined. PROPRIETARY AND CONFIDENTIAL ISSUE 4 M13 DS3, DS2, E1 TU12 1,1,1 1,1,1 1,2,1 1,1,2 1,3,1 1,1,3 1,4,1 1,2,1 1,5,1 1,2,2 1,6,1 1,2,3 1,7,1 1,3,1 1,1,2 1,3,2 1,2,2 1,3,3 1,3,2 1,4,1 1,4,2 1,4,2 1,5,2 1,4,3 1,6,2 1,5,1 1,7,2 1,5,2 1,1,3 1,5,3 1,2,3 1,6,1 1,3,3 1,6,2 1,4,3 1,6,3 1,5,3 1,7,1 1,6,3 1,7,2 1,7,3 1,7,3 2,1,1 2,1,1 ... ... 75 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX H-MVIP port index, E1 1,1 1,2 1,3 1,4 2,1 2,2 2,3 2,4 3,1 3,2 3,3 3,4 4,1 4,2 4,3 4,4 5,1 5,2 5,3 5,4 6,1 8,1 ... ...
Page 89
... Programmed codes can be from three to eight bits in length. The code sequence detection and timing is compatible with the specifications defined in T1.403, TR-TSY-000312, and TR-TSY-000303. PROPRIETARY AND CONFIDENTIAL ISSUE 4 76 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 90
... By definition, RAI- repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of 00000000 11111111 (right-to-left) with 00111110 11111111. PROPRIETARY AND CONFIDENTIAL ISSUE 4 th code (111111) is similar to the HDLC 77 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate. ...
Page 91
... CAS multiframe). Moreover, the framer also extracts submultiframe-aligned 4-bit codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessor-accessible registers that are updated every CRC submultiframe. PROPRIETARY AND CONFIDENTIAL ISSUE 4 78 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 92
... The algorithm provides robust framing operation even in the presence of random bit errors; the algorithm provides a 99.98% probability of finding frame alignment within the presence of 10 PROPRIETARY AND CONFIDENTIAL ISSUE 4 -3 bit error rate and no mimic patterns. 79 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 93
... CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed non CRC-4 interface. The details of this algorithm are illustrated in the state diagram in Figure 9. PROPRIETARY AND CONFIDENTIAL ISSUE 4 80 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate the ...
Page 94
... BFA_Par 8m s expire and NOT(400m s expire) CRCMFA_Par CRC to non-CRC Interworking CR CMFA_Par (Optional setting) 81 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX NFAS not found next fram e FAS not found next fram e Start 8m s tim er 400m s ...
Page 95
... CRC-to-non-CRC interworking. In this mode, the E1 framer may be PROPRIETARY AND CONFIDENTIAL ISSUE 4 Out of Frame Yes Yes Yes PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Out of Offline Frame Yes Yes Yes No No ...
Page 96
... CAS multiframes. Loss of CAS multiframe alignment is also declared if basic frame alignment has been lost. PROPRIETARY AND CONFIDENTIAL ISSUE 4 83 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 97
... T1/E1 Performance Monitoring CRC error events, Frame Synchronization bit error events, and Out Of Frame events, or optionally, Change of Frame Alignment (COFA) events are PROPRIETARY AND CONFIDENTIAL ISSUE 4 -3 mean bit error rate. 84 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 98
... FIFO. On end of message, the RHDL Indirect Channel Data Registers indicates the FCS status and if the packet contained a non-integer number of bytes. PROPRIETARY AND CONFIDENTIAL ISSUE 4 error for SF and SLC96 and PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX error for ESF framing e ...
Page 99
... This code is set to all 1’s when the ELST is reset. 9.8 T1/E1 Signaling Extraction Channel associated signaling (CAS) is extracted from an E1 signaling multi- frame or from ESF, SLC96 and SF T1 formats. PROPRIETARY AND CONFIDENTIAL ISSUE 4 86 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 100
... T1 Transmitter The T1 transmitter generates the 1.544 Mbit/s T1 data streams according to SF, SLC96 or ESF frame formats. PROPRIETARY AND CONFIDENTIAL ISSUE 4 87 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 101
... LOOPT and REFSEL context bits logic 0). With an H-MVIP interface, the transmit elastic store cannot be bypassed, so the transmit clock must be locked to CTCLK which must be presented a clock that is locked to CMV8MCLK. PROPRIETARY AND CONFIDENTIAL ISSUE 4 88 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 102
... E1 Sa-bit data link. The data link may also be presented in any sub-set of bits within a selected DS0. The HDLC transmitter is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, PROPRIETARY AND CONFIDENTIAL ISSUE 4 89 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 103
... link and the ingress interface and the other between the egress interface and the transmit link to be multiplexed into DS3 or mapped into SONET/SDH. Each jitter attenuator receives jittered PROPRIETARY AND CONFIDENTIAL ISSUE 4 90 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 104
... Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For T1 modes the jitter attenuator input jitter tolerance is 48 Unit Intervals PROPRIETARY AND CONFIDENTIAL ISSUE 4 91 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 105
... Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 369 Hz. Figure 10 - Jitter Tolerance T1 Modes 100 28 10 1.0 0.1 0.01 1 4.9 PROPRIETARY AND CONFIDENTIAL ISSUE 4 10 100 300 Jitter Frequency (Hz) 92 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Minimum Jitter Tolerance 62411Min acceptable unacceptable 1k 10k 100k 48 0.4 ...
Page 106
... Jitter frequencies above 3.4 Hz are attenuated at a level per decade, as shown in Figure 12. PROPRIETARY AND CONFIDENTIAL ISSUE 100 Jitter Frequency (Hz) 93 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Minimum Jitter Tolerance ITU-T G.823 Min acceptable unacceptable 1k 2.4k 10k ...
Page 107
... Jitter frequencies above 2.5 Hz are attenuated at a level per decade, as shown in Figure 13. PROPRIETARY AND CONFIDENTIAL ISSUE 4 Jitter Attenuator Response 43802 Max 62411 Max 20 350 100 1k Jitter Frequency (Hz) 94 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 10k 100k ...
Page 108
... The tracking range is 2.048 MHz ± 999 Hz with no jitter or SREFCLK frequency offset. PROPRIETARY AND CONFIDENTIAL ISSUE 4 G.737, G.738, G.739, G.742 Max Jitter Attenuator Response 40 400 10 100 Jitter Frequency (Hz) 95 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX unacceptable acceptable 1k 10k 100k ...
Page 109
... RDATO[x], mapped into the SBI bus or may be demultiplexed to 28 DS1s or 21 E1s (ITU-T Rec. G.747). PROPRIETARY AND CONFIDENTIAL ISSUE bits or any user programmable bit pattern from bits 96 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX - ...
Page 110
... Three DS3 maintenance signals (a RED alarm condition, the alarm indication signal, and the idle signal) are detected by the DS3-FRMR. The maintenance PROPRIETARY AND CONFIDENTIAL ISSUE 4 97 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 111
... LOS, OOF or RED, or AIS. The DS3-FRMR can also be enabled to automatically insert C-bit Parity FEBE upon detection of receive C-bit parity error. PROPRIETARY AND CONFIDENTIAL ISSUE 4 98 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 bit error rate. For AIS, ...
Page 112
... FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching. PROPRIETARY AND CONFIDENTIAL ISSUE 4 Th code (111111) is similar to the HDLC flag 99 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 113
... If the holding registers have not been read since the last interrupt, an overrun status bit is set. In addition, a register is provided to indicate changes in the PMON counters since the last accumulation interval. PROPRIETARY AND CONFIDENTIAL ISSUE 4 100 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 114
... The code to be transmitted is programmed by writing to the XBOC code registers when it is held until the latest code has been transmitted at least 10 PROPRIETARY AND CONFIDENTIAL ISSUE 4 101 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 115
... HDLC transmitter data FIFO underflows, an abort sequence is automatically transmitted. When enabled, the HDLC transmitter continuously transmits the flag sequence (01111110) until data is ready to be transmitted. PROPRIETARY AND CONFIDENTIAL ISSUE 4 102 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 116
... The PRGD can be programmed to generate any pseudo-random pattern with 32 length bits or any user programmable bit pattern from bits in PROPRIETARY AND CONFIDENTIAL ISSUE 4 103 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 117
... DS2 payload loopback can be activated or deactivated under software control. During payload loopback the DS2 stream being looped back still continues unaffected in the demultiplex direction to the DS2 Framer. All seven PROPRIETARY AND CONFIDENTIAL ISSUE 4 104 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 118
... When an OOF occurs, the FERF value is held at the state contained in the last buffer location PROPRIETARY AND CONFIDENTIAL ISSUE 4 105 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -3 . Each "valid" DS2 M- ...
Page 119
... C3 being the inverse of C1 and C2. Because TR-TSY- 000233 Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. As PROPRIETARY AND CONFIDENTIAL ISSUE 4 106 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 120
... G.832 format). While in-frame, the E3-FRMR also extracts various overhead bytes and processes them according to the framing format selected: PROPRIETARY AND CONFIDENTIAL ISSUE 4 107 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 121
... Once the framer has determined the new frame alignment, the out-of-frame indication is removed and a COFA indication is declared if the new alignment differs from the previous alignment. PROPRIETARY AND CONFIDENTIAL ISSUE 4 108 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 122
... In G.832 E3 format, the E3-TRAN: • inserts the BIP-8 byte calculated over the preceding frame; • inserts the Trail Trace bytes; PROPRIETARY AND CONFIDENTIAL ISSUE 4 -3 BER as 92.9% in G.832 and 98.0% in G.751. 109 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 123
... Further, the E3-TRAN can provide insertion of bit errors in the framing pattern or in the parity bits, and insertion of single line code violations for diagnostic purposes. PROPRIETARY AND CONFIDENTIAL ISSUE 4 110 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 124
... Alarms are raised to indicate reception of unstable and mismatched messages. In the transmit direction, the trail trace message is sourced from the internal RAM for insertion into the TR byte by the E3-TRAN. PROPRIETARY AND CONFIDENTIAL ISSUE 4 111 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 125
... The pointer interpreter is a time-sliced state machine that can process independent tributaries. The state vector is saved in RAM as directed by the incoming timing generator. The pointer interpreter processes the incoming PROPRIETARY AND CONFIDENTIAL ISSUE 4 112 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 126
... On a per tributary basis, tributary path AIS and tributary idle (unequipped) can be inserted as controlled by microprocessor accessible registers. The idle code is selectable globally for the entire VC3 or PROPRIETARY AND CONFIDENTIAL ISSUE 4 113 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 127
... RFI is recognized when bit set high for five or ten consecutive frames. The RDI and RFI bits may be PROPRIETARY AND CONFIDENTIAL ISSUE 4 114 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 128
... XXX ≠ 000, 001, PDI Code 000 001 PDI Code XXX ≠ 000, 001, PDI Code 000 001 XXX YYY 115 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX PSLM State Match Mismatch Mismatch Mismatch Mismatch Match Match ...
Page 129
... Each one of three Receive Tributary Demappers (RTDM) demaps bit asynchronous mapped signals from an STS-1 SPE, TUG3 within a STM-1/VC4 or STM-1 VC3 payload. The bit asynchronous T1 mapping consists PROPRIETARY AND CONFIDENTIAL ISSUE 4 116 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 130
... C: Stuff Control bit - set to logic ‘1’ for stuff indication S: Stuff Opportunity bit - when stuff control bit is ‘0’, stuff opportunity is I bit O: Overhead I: T1 payload information PROPRIETARY AND CONFIDENTIAL ISSUE 117 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 131
... The RTDM performs majority voting on the tributary stuff control (C1, C2) bits. If the majority of each set of the stuff control bits indicate a stuff operation, then the associated stuff opportunity bit (S1, S2) will not carry payload. PROPRIETARY AND CONFIDENTIAL ISSUE 4 1 118 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 132
... RAWSIG bit programmed through the SIGX Indirect Channel Data registers is logic 1. This is programmed on a per-tributary basis. For E1, the signaling is extracted from “Multiframe alignment signal” byte. PROPRIETARY AND CONFIDENTIAL ISSUE 4 The demapping is done 119 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX bit ...
Page 133
... CCRRRRRR CCRRRRRR CCRRRRRR CCRRRRRR 120 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX CCRROORS CCRROORS ...
Page 134
... (0) F ( (0) F ( (0) F (0) C (0) 121 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX (1) ...
Page 135
... DS3 AIS, faster and slower status. The faster pattern is used to drain the elastic store to avoid overflows. The slower pattern is used to allow the elastic store to fill to avoid underflows. PROPRIETARY AND CONFIDENTIAL ISSUE 4 122 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 136
... An PROPRIETARY AND CONFIDENTIAL ISSUE 4 Run Faster 621 621 622 621 621 622 621 621 622 123 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Run Slower 621 621 621 621 622 622 621 621 622 621 ...
Page 137
... Telecom Drop bus, LDDATA[7:0]. The contents of the SONET/SDH Master Tributary Remote Defect Indication Control register determine which alarms PROPRIETARY AND CONFIDENTIAL ISSUE 4 124 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 138
... UI. To reduce mapping jitter even further, a dither technique is inserted between the control loop and the stuff bit generator resulting in an acceptable desynchronizer mapping jitter of about 0.3 UI. PROPRIETARY AND CONFIDENTIAL ISSUE 4 125 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 139
... SPE mapped payload capacity. The asynchronous DS3 mapping consists of 9 rows every 125 µs (8 KHz). Each row contains 621 information bits, 5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication PROPRIETARY AND CONFIDENTIAL ISSUE 4 126 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 140
... The 8 kHz STS-1 (STM-0/AU3) frame interval is subdivided into 9 rows. Each row contains one stuff opportunity. Table 8 illustrates the stuffing implementation where S means stuff bit and I means an information bit (DS3 data). PROPRIETARY AND CONFIDENTIAL ISSUE 4 127 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 141
... H-MVIP, SBI bus and SBI bus with CAS or CCS H- MVIP. PROPRIETARY AND CONFIDENTIAL ISSUE 4 Normal or DS3 AIS Run Faster 128 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Run Slower ...
Page 142
... Interface with CAS or CCS H-MVIP Interface”. PROPRIETARY AND CONFIDENTIAL ISSUE 4 ELST T1/E1Transmitte r: Elastic Frame Gene ration, Store Alarm Insertion, Signaling Insertion, Trunk Conditioning 129 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX TRANSMITTER TJAT to DS3 Digital PLL Multiplexer or TJAT SONET/SDH FIFO Mapper ...
Page 143
... T1s or 63 E1s. The H-MVIP PROPRIETARY AND CONFIDENTIAL ISSUE 4 ELST Elastic Store T1/E1 FRM R Framer: Fram e Alignmen t, Alarm Extraction 130 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX RECEIVER RJAT From DS3 Digital Jitter Multiplexer or Attenuator SONET/SDH m apper ...
Page 144
... When accessing the CAS or CCS signaling via the H-MVIP interface in parallel with the SBI interface a receive signaling elastic store is used to adapt any timing differences between the data interface and the CAS or CCS H-MVIP interface. PROPRIETARY AND CONFIDENTIAL ISSUE 4 131 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 145
... Failure of the source to respond to these commands will ultimately result in overflows or underflows which can be configured to generate per link interrupts. PROPRIETARY AND CONFIDENTIAL ISSUE 4 132 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 146
... The frame slip buffer (ELST) must be in the datapath in “locked” mode. PROPRIETARY AND CONFIDENTIAL ISSUE 4 ELST Elastic Store T1/E1 FRM R Framer: Fram e Alignmen t, Alarm Extraction 133 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX RECEIVER RJAT From DS3 Digital Jitter Multiplexer or Attenuator SONET/SDH m apper ...
Page 147
... The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The TEMUX-84 identification code is 083160CD hexadecimal. PROPRIETARY AND CONFIDENTIAL ISSUE 4 134 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 148
... Revision Global Reset Global Configuration SPE #1 Configuration SPE #2 Configuration SPE #3 Configuration Bus Configuration Global Performance Monitor Update Reference Clock Select Recovered Clock#1 Select Recovered Clock#2 Select Recovered Clock#3 Select 135 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 149
... Master SBIDET1 Collision Detect LSB Master SBIDET1 Collision Detect MSB T1/E1 Master Configuration T1/E1 PRGD #1 Tributary Select T1/E1 PRGD #2 Tributary Select T1/E1 PRGD #3 Tributary Select T1/E1 PRGD #4 Tributary Select T1/E1 PRGD #5 Tributary Select T1/E1 PRGD #6 Tributary Select 136 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 150
... RX-MVIP-ELST Idle Code RX-MVIP-ELST Slip Status RX-MVIP-ELST Slip Direction RX-MVIP-ELST Slip Interrupt Enable RX-SBI-ELST Indirect Status RX-SBI-ELST Indirect Channel Address Register RX-SBI-ELST Indirect Channel Data Register RX-SBI-ELST Idle Code 137 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 151
... THDL Indirect Status THDL Indirect Channel Address Register THDL Indirect Channel Data Registers THDL Interrupt Status SIGX Indirect Status/Time-slot Address SIGX Indirect Channel Address Register SIGX Indirect Channel Data Registers 138 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 152
... Extract External ReSynch Interrupt Status INSBI Control INSBI FIFO Underrun Interrupt Status INSBI FIFO Overrun Interrupt Status INSBI Tributary Indirect Access Address INSBI Tributary Indirect Access Control INSBI Tributary Control Indirect Access Data 139 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 153
... DS3/E3 PMON Line Code Violation Event Count MSB DS3/E3 PMON Framing Bit Error Event Count LSB DS3/E3 PMON Framing Bit Error Event Count MSB DS3 PMON Excessive Zeros LSB 140 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 154
... DS3/E3 RDLC Secondary Address Match PRGD Control PRGD Interrupt Enable/Status PRGD Length PRGD Tap PRGD Error Insertion PRGD Pattern Insertion #1 PRGD Pattern Insertion #2 PRGD Pattern Insertion #3 PRGD Pattern Insertion #4 141 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 155
... DS2 FRMR #1 FERR Count DS2 FRMR #1 PERR Count (LSB) DS2 FRMR #1 PERR Count (MSB) MX12 #1Configuration and Control MX12 #1 Loopback Code Select MX12 #1 Mux/Demux AIS Insert MX12 #1 Loopback Activate MX12 #1 Loopback Interrupt 142 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 156
... E3 TRAN Status and Diagnostic Options E3 TRAN BIP-8 Error Mask E3 TRAN Maintenance and Adaptation Options TTB Control TTB Trail Trace Identifier Status TTB Indirect Address TTB Indirect Data TTB Expected Payload Type Label 143 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 157
... T1/E1 Pattern Generator and Detector Pattern Insertion #1 T1/E1 Pattern Generator and Detector Pattern Insertion #2 T1/E1 Pattern Generator and Detector Pattern Insertion #3 T1/E1 Pattern Generator and Detector Pattern Insertion #4 T1/E1 Pattern Generator and Detector Pattern Detector #1 144 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 158
... Generator Controller Channel Indirect Data Buffer Receiver Controller Configuration Receiver Controller µP Access Status Receiver Controller Channel Indirect Address/Control Receiver Controller Channel Indirect Data Buffer SONET/SDH Master Reset SONET/SDH Master Ingress Configuration 145 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 159
... VTPP Ingress TUG2 #1 to TUG2 #7, Configuration and Status VTPP Ingress TUG2 #1 to TUG2 #7, Alarm Status VTPP Ingress TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Ingress TUG2 #1 to TUG2 #7, AIS Interrupt 146 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 160
... VTPP Ingress TUG2 #1 to TUG2 #7, Configuration and Status VTPP Ingress TUG2 #1 to TUG2 #7, Alarm Status VTPP Ingress TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Ingress TUG2 #1 to TUG2 #7, AIS Interrupt 147 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 161
... VTPP Egress TUG2 #1 to TUG2 #7, Configuration and Status VTPP Egress TUG2 #1 to TUG2 #7, Alarm Status VTPP Egress TUG2 #1 to TUG2 #7, LOP Interrupt VTPP Egress TUG2 #1 to TUG2 #7 AIS Interrupt 148 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 162
... Access Address Register Byte Synchronous Mapping Tributary Indirect Access Control Register Byte Synchronous Mapping Tributary Mapping Indirect Access Data Register Byte Synchronous Mapping Tributary Control Indirect Access Data Register 149 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 163
... Alarm Status RTOP TUG2 #1 to TUG2 #7, Expected Path Signal Label RTOP TUG2 #1 to TUG2 #7, Accepted Path Signal Label RTOP TUG2 #1 to TUG2 #7, BIP-2 Error Count LSB 150 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 164
... RTOP TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration RTOP TUG2 #1 to TUG2 #7, Configuration RTOP TUG2 #1 to TUG2 #7, Configuration and Alarm Status RTOP TUG2 #1 to TUG2 #7, Expected Path Signal Label 151 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 165
... RTOP TUG2 #1 to TUG2 #7, RDI Interrupt RTOP TUG2 #1 to TUG2 #7, RFI Interrupt RTOP TUG2 #1 to TUG2 #7, Inband Error Reporting Configuration RTOP TUG2 #1 to TUG2 #7, Configuration 152 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 166
... Interrupt RTOP TUG2 #1 to TUG2 #7, PSLM Interrupt RTOP TUG2 #1 to TUG2 #7, PSLU Interrupt RTOP TUG2 #1 to TUG2 #7, RDI Interrupt RTOP TUG2 #1 to TUG2 #7, RFI Interrupt 153 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 167
... RTOP TUG2 #1 to TUG2 #7, BIP-2 Error Count MSB RTOP TUG2 #1 to TUG2 #7, FEBE Error Count LSB RTOP TUG2 #1 to TUG2 #7, FEBE Error Count MSB RTOP TUG2 #1 to TUG2 #7, COPSL Interrupt 154 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 168
... Control TRAP TUG2 #1 to TUG2 #7 of TUG3 #1, Egress AIS Control TRAP TUG2 #1 to TUG2 #7 of TUG3 #2, Control TRAP TUG2 #1 to TUG2 #7 of TUG3 #2, Egress AIS Control 155 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 169
... TRAP TUG2 #1 to TUG2 #7 of TUG3 #3, Egress AIS Control TRAP Indirect Remote Alarm Page Address TRAP Indirect Remote Alarm Tributary Address TRAP Indirect Datapath Tributary Data TRAP RDI Control 156 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 170
... Control TTOP TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control TTOP TUG2 #1 to TUG2 #7 of TUG3 #2, Control TTOP TUG2 #1 to TUG2 #7 of TUG3 #2, BIP Diagnostic Control 157 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 171
... TTOP Indirect Trail Trace Identifier Tributary Select TTOP Indirect Trail Trace Identifier Buffer Address TTOP Indirect Trail Trace Identifier Buffer Data TTMP Tributary Control TTMP Time Switch Page Control 158 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 172
... RTTB TUG2 #1 to TUG2 #7, Configuration and Status RTTB TUG2 #1 to TUG2 #7, Configuration and Status RTTB TU3 TUG2 #1 to TUG2 #7, TIM Interrupt RTTB TUG2 #1 to TUG2 #7, TIM Interrupt 159 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 173
... RTTB TUG2 #1 to TUG2 #7, TIU Interrupt RTTB TUG2 #1 to TUG2 #7, TIU Interrupt RTTB TIU Threshold RTTB Indirect Tributary Select RTTB Indirect Address Select RTTB Indirect Data Select RTTB #2 RTTB #3 Master Test 160 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 174
... Writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4) Writing into read-only normal mode register bit locations does not affect TEMUX-84 operation unless otherwise noted. PROPRIETARY AND CONFIDENTIAL ISSUE 4 161 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 175
... Writeable register bits are not initialized upon reset unless otherwise noted. PROPRIETARY AND CONFIDENTIAL ISSUE 4 162 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 176
... When PMCTST is logic 0, the DBCTRL bit is ignored. Reserved These bits must be logic 0 for correct operation. PROPRIETARY AND CONFIDENTIAL ISSUE 4 Function Default Reserved 0 Unused X Unused X PMCTST 0 DBCTRL X Reserved 0 HIZDATA X HIZIO 0 163 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 177
... HIZIO bit is a logic 1, all output pins of the TEMUX-84, except the data bus, are held in a high-impedance state. While the HIZDATA bit is a logic 1, the data bus is held in a high-impedance state which inhibits microprocessor read cycles. PROPRIETARY AND CONFIDENTIAL ISSUE 4 164 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 178
... Length Version number Part Number Manufacturer's identification code Device identification PROPRIETARY AND CONFIDENTIAL ISSUE 4 Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111 32 bits 0x0 0x8316 0x0CD 0x083160CD 165 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 179
... OUT_CELL - A_8 20 OUT_CELL - A_9 21 OUT_CELL - A_10 22 OUT_CELL - A_11 23 OUT_CELL - A_12 24 OUT_CELL - WRB 166 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Bit # Cell Type Id Bit 151 OUT_CELL - 152 IO_CELL - 153 OUT_CELL - 154 IO_CELL - 155 OUT_CELL - 156 IO_CELL - 157 ...
Page 180
... IN_CELL - LAC1J1V1 52 IN_CELL - OEB_LAC1J1V1 53 IN_CELL - LAC1 54 IN_CELL - CLK52M 55 IN_CELL - RADWEST 56 IN_CELL - RADWESTFP 167 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Bit # Cell Type Id Bit 176 IN_CELL - 177 IN_CELL - 178 OUT_CELL - 179 OUT_CELL - 180 OUT_CELL - 181 OUT_CELL - 182 ...
Page 181
... OUT_CELL - OEB_TPOS_TDAT_1 83 OUT_CELL - TICLK_1 84 OUT_CELL - RNEG_RLCV_1 85 OUT_CELL - RPOS_RDAT_1 86 OUT_CELL - RCLK_1 87 OUT_CELL - TNEG_TMFP_2 168 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Bit # Cell Type Id Bit 208 IN_CELL - 209 IN_CELL - 210 IN_CELL - 211 IN_CELL - 212 IN_CELL - 213 IN_CELL - 214 ...
Page 182
... OUT_CELL - ROVRHD_1 112 OUT_CELL - OEB_ROVRHD_1 113 OUT_CELL - RFPO_RMFPO_1 114 IN_CELL - OEB_RFPO_RMFPO_1 115 IN_CELL - TFPO_TMFPO_ TGAPCLK_1 169 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Bit # Cell Type Id Bit 239 OUT_CELL - 240 OUT_CELL - 241 OUT_CELL - 242 OUT_CELL - 243 OUT_CELL ...
Page 183
... TFPO_TMFPO_ TGAPCLK_3 140 IN_CELL - OEB_TFPO_TMFPO_ TGAPCLK_3 141 IN_CELL - TFPI_TMFPI_3 142 OUT_CELL - TDATI_3 143 OUT_CELL - RECVCLK_3 170 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Bit # Cell Type Id Bit 267 OUT_CELL - 268 IN_CELL - 269 IN_CELL - 270 OUT_CELL 1 271 OUT_CELL ...
Page 184
... IO_CELL - OEB_RECVCLK_2 147 OUT_CELL - RECVCLK_1 148 IO_CELL - OEB_RECVCLK_1 149 OUT_CELL - XCLK_E1 150 IO_CELL - XCLK_T1 171 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX Bit # Cell Type Id Bit 295 OUT_CELL 0 296 OUT_CELL 0 297 OUT_CELL 1 298 OUT_CELL 0 299 OUT_CELL ...
Page 185
... SBI LINK # 2.048Mbit/s SBI LINK # PROPRIETARY AND CONFIDENTIAL ISSUE 4 = 7*(TU11-1) + TUG2 = 4*(DS2-1)+DS1 = 4*(MVED index – 7*SPE - 1) + DS1 = 7*(TU12-1) + TUG2 = 3*(DS2-1)+E1 = 4*(MVED index – 7*SPE - 172 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 186
... PMC-1991437 Table 13 - Indexing for 1.544 Mbit/s Tributaries SBI Bus Telecom Bus SPE, LINK TUG-3, TUG-2, 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 1,10 1,11 1,12 1,13 1,14 1,15 1,16 1,17 1,18 1,19 1,20 1,21 1,22 1,23 1,24 1,25 1,26 1,27 1,28 2,1 ... PROPRIETARY AND CONFIDENTIAL ISSUE 4 M13 DS3, DS2, TU11 DS1 1,1,1 1,1,1 1,2,1 1,1,2 1,3,1 1,1,3 1,4,1 1,1,4 1,5,1 1,2,1 1,6,1 1,2,2 1,7,1 1,2,3 1,1,2 1,2,4 1,2,2 1,3,1 1,3,2 1,3,2 1,4,2 1,3,3 1,5,2 1,3,4 1,6,2 1,4,1 1,7,2 1,4,2 1,1,3 1,4,3 1,2,3 1,4,4 1,3,3 1,5,1 1,4,3 1,5,2 1,5,3 1,5,3 1,6,3 1,5,4 1,7,3 1,6,1 1,1,4 1,6,2 1,2,4 1,6,3 1,3,4 1,6,4 1,4,4 1,7,1 1,5,4 1,7,2 1,6,4 1,7,3 1,7,4 1,7,4 2,1,1 2,1,1 ... ... 173 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX H-MVIP port index, DS1 1,1 1,2 1,3 1,4 2,1 2,2 2,3 2,4 3,1 3,2 3,3 3,4 4,1 4,2 4,3 4,4 5,1 5,2 5,3 5,4 6,1 6,2 6,3 6,4 7,1 7,2 7,3 7,4 8,1 ... ...
Page 187
... SBI and Telecom Buses Both 19.44 MHz The rising and falling edges of LREFCLK must be aligned with a tolerance of +/- 10ns to the corresponding edges of SREFCLK. PROPRIETARY AND CONFIDENTIAL ISSUE 4 M13 DS3, DS2, E1 TU12 1,1,1 1,1,1 1,2,1 1,1,2 1,3,1 1,1,3 1,4,1 1,2,1 1,5,1 1,2,2 1,6,1 1,2,3 1,7,1 1,3,1 1,1,2 1,3,2 1,2,2 1,3,3 1,3,2 1,4,1 1,4,2 1,4,2 1,5,2 1,4,3 1,6,2 1,5,1 1,7,2 1,5,2 1,1,3 1,5,3 1,2,3 1,6,1 1,3,3 1,6,2 1,4,3 1,6,3 1,5,3 1,7,1 1,6,3 1,7,2 1,7,3 1,7,3 2,1,1 2,1,1 ... ... 174 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX H-MVIP port index, E1 1,1 1,2 1,3 1,4 2,1 2,2 2,3 2,4 3,1 3,2 3,3 3,4 4,1 4,2 4,3 4,4 5,1 5,2 5,3 5,4 6,1 8,1 ... ...
Page 188
... ISSUE 4 Clock Cycles LAC1 leads SDC1FP ( 2…) LSTM[1: 4n (Clock Cycles LAC1 leads SDC1FP) mod 4 175 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 189
... MHz SBI to 19.44 MHz Telecom to Bus Alignment Options SSTM[1:0] 00 PROPRIETARY AND CONFIDENTIAL ISSUE 4 LREFCLK Cycles LAC1 sampling edge leads SREFCLK rising edge SREFCLK Cycles SDC1FP sampling edge leads LREFCLK rising edge 1 176 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 190
... The T1/E1 transmit clock must be referenced to CTCLK. For H-MVIP, CTCLK must be frequency locked to CMVFPB. For SBI, CTCLK PROPRIETARY AND CONFIDENTIAL ISSUE and must know the multiframe 177 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 191
... A and B bits: 0110, 1100, 0011, 1001.) An interrupt on change of signaling will only occur if the collected ABCD state changes, but not just from toggling bits. PROPRIETARY AND CONFIDENTIAL ISSUE 4 178 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 192
... 179 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 84 bits 84 bits 84 bits ...
Page 193
... Read the bits of the TEMUX-84 Master Interrupt Source register (0x0010) to identify which of the 14 interrupt registers (0x0011-0x001E) needs to be read to identify the interrupt. For example, a logic one read in the DS3E3INT PROPRIETARY AND CONFIDENTIAL ISSUE 4 180 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 194
... Table 18 for E1 mode, and in Table 19 for T1 mode. Table 18 - PMON Counter Saturation Limits (E1 mode) Counter BER FER 4 CRCE cannot saturate FEBE cannot saturate PROPRIETARY AND CONFIDENTIAL ISSUE 4 -3 181 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 195
... PROPRIETARY AND CONFIDENTIAL ISSUE 4 Format BER ESF - ESF cannot saturate -3 , the average counter event count 50 100 150 Framing Bit Error Count Per Second 182 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 200 250 -4 , ...
Page 196
... CRCE ÷ 8000 ç è ç 256 ç ç è 200 400 600 CRCE 183 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX -4 , each CRC-4 error is often 800 1000 1200 ...
Page 197
... CRC-6 error is often due to more than one æ ö æ 24 ö ç − log ç 1 BEE ÷ ç è 8000 ç 193 ç ç è 184 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 200 250 -4 , there tends ...
Page 198
... PROPRIETARY AND CONFIDENTIAL ISSUE 4 100 150 200 250 CRCE Average Count Over Many 1 Second Intervals 200 400 600 Bit Error Event Count Per Second 185 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX 300 350 800 1000 1200 ...
Page 199
... TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic interrupt on INTB is generated upon detection of a PROPRIETARY AND CONFIDENTIAL ISSUE 4 186 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...
Page 200
... If OVRI=1, then the FIFO has overflowed. The packet of which the last byte written into the FIFO belongs to, has been corrupted and must be PROPRIETARY AND CONFIDENTIAL ISSUE 4 187 PM8316 TEMUX-84 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX ...