UPD78F9468GB-8ET NEC, UPD78F9468GB-8ET Datasheet
UPD78F9468GB-8ET
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UPD78F9468GB-8ET Summary of contents
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User’s Manual µ PD789467 Subseries 8-Bit Single-Chip Microcontrollers µ PD789462 µ PD789464 µ PD789466 µ PD789467 µ PD78F9468 Document No. U15552EJ2V1UD00 (2nd edition) Date Published January 2004 N CP(K) c Printed in Japan ...
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User’s Manual U15552EJ2V1UD ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • ...
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... Addition of recommended oscillator constants for mask ROM versions • Modification of Write and Erase Characteristics p. 212 Addition of recommended conditions for SOLDERING CONDITIONS p. 217 Change of name “conversion connector” and “conversion socket” to “conversion adapter (TGB-052SBP)” in A.5 Debugging Tools (Hardware) p. 224 Addition of APPENDIX C REVISION HISTORY 6 Major Revisions in This Edition Description µ ...
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Target Readers This manual is intended for users who wish to understand the functions of the µ PD789467 Subseries and to design and develop application systems and programs using these microcontrollers. Target products: • Purpose This manual is intended to ...
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices µ PD789467 Subseries User’s Manual 78K/0S Series Instructions User’s Manual Documents Related to Development Tools ...
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... NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html) Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing ...
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... SS µ 2.2. PD78F9468 only) ................................................................................................................ 35 PP 2.2.16 IC0 (mask ROM version only) ....................................................................................................... 35 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................36 CHAPTER 3 CPU ARCHITECTURE ......................................................................................................38 3.1 Memory Space............................................................................................................................38 3.1.1 Internal program memory space ................................................................................................... 43 3.1.2 Internal data memory (internal high-speed RAM) space ............................................................... 44 3.1.3 Special-function register (SFR) area ............................................................................................. 44 3.1.4 Data memory addressing .............................................................................................................. 45 3 ...
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... Clock Generator Configuration ................................................................................................ 76 5.3 Registers Controlling Clock Generator ................................................................................... 78 5.4 System Clock Oscillators.......................................................................................................... 80 5.4.1 Main system clock oscillator.......................................................................................................... 80 5.4.2 Subsystem clock oscillator ............................................................................................................ 81 5.4.3 Example of incorrect resonator connection ................................................................................... 82 5.4.4 Divider........................................................................................................................................... 83 5.4.5 When no subsystem clock is used ................................................................................................ 83 5.5 Clock Generator Operation....................................................................................................... 84 5.6 Changing Setting of System Clock and CPU Clock ............................................................... 85 5.6.1 Time required for switching between system clock and CPU clock............................................... 85 5 ...
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Registers Controlling 8-Bit Timers 30 and 40 .........................................................................93 6.4 Operation of 8-Bit Timers 30 and 40 ........................................................................................98 6.4.1 Operation as 8-bit timer counter.................................................................................................... 98 6.4.2 Operation as 16-bit timer counter................................................................................................ 105 6.4.3 Operation as carrier generator .................................................................................................... 109 6.4.4 ...
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... Flash Memory Characteristics................................................................................................182 15.1.1 Programming environment.......................................................................................................... 182 15.1.2 Communication mode ................................................................................................................. 183 15.1.3 On-board pin processing............................................................................................................. 185 15.1.4 Connection on flash memory writing adapter .............................................................................. 188 CHAPTER 16 MASK OPTION .............................................................................................................189 CHAPTER 17 INSTRUCTION SET ......................................................................................................190 17.1 Operation ..................................................................................................................................190 17.1.1 Operand identifiers and description methods .............................................................................. 190 17.1.2 Description of “Operation” column............................................................................................... 191 17.1.3 Description of “ ...
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CHAPTER 18 ELECTRICAL SPECIFICATIONS.................................................................................200 CHAPTER 19 PACKAGE DRAWING ..................................................................................................211 CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS...........................................................212 APPENDIX A DEVELOPMENT TOOLS...............................................................................................213 A.1 Software Package ....................................................................................................................215 A.2 Language Processing Software .............................................................................................215 A.3 Control Software ......................................................................................................................216 A.4 Flash Memory Writing Tools ...................................................................................................217 A.5 Debugging Tools ...
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... Format of Processor Clock Control Register ................................................................................................. 78 5-3 Format of Suboscillation Mode Register ........................................................................................................ 79 5-4 Format of Subclock Control Register ............................................................................................................. 79 5-5 External Circuit of Main System Clock Oscillator ........................................................................................... 80 5-6 External Circuit of Subsystem Clock Oscillator .............................................................................................. 81 5-7 Examples of Incorrect Resonator Connection................................................................................................ 82 5-8 Example of Switching Between System Clock and CPU Clock ..................................................................... 86 LIST OF FIGURES (1/4) Title PD789462) ........................................................................................................ 45 PD789464) ........................................................................................................ 46 PD789466) ........................................................................................................ 47 PD789467) ........................................................................................................ 48 PD78F9468)...................................................................................................... 49 User’ ...
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Figure No. 6-1 Block Diagram of Timer 30 ............................................................................................................................ 89 6-2 Block Diagram of Timer 40 ............................................................................................................................ 90 6-3 Block Diagram of Output Controller (Timer 40) .............................................................................................. 91 6-4 Format of 8-Bit Timer Mode Control Register 30 ........................................................................................... 94 6-5 ...
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... Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs .................... 146 10-7 Common Signal Waveforms ........................................................................................................................ 148 10-8 Voltages and Phases of Common and Segment Signals............................................................................. 148 10-9 Four-Time-Slice LCD Display Pattern and Electrode Connections .............................................................. 149 10-10 Example of Connecting Four-Time-Slice LCD Panel ................................................................................... 150 10-11 Examples of Four-Time-Slice LCD Drive Waveform.................................................................................... 151 10-12 Example of Pin Connection for LCD Driver ...
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... Reset Timing by RESET Input in STOP Mode............................................................................................. 177 14-5 Reset Timing by Power-on Clear ................................................................................................................. 178 15-1 Environment for Writing Program to Flash Memory ..................................................................................... 182 15-2 Communication Mode Selection Format ...................................................................................................... 183 15-3 Example of Connection with Dedicated Flash Programmer ......................................................................... 184 15-4 V Pin Connection Example ....................................................................................................................... 185 PP 15-5 Signal Conflict (Input Pin of Serial Interface) ............................................................................................... 186 15-6 Abnormal Operation of Other Device ...
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... Table No. 2-1 Types of Pin I/O Circuits and Recommended Connection of Unused Pins.................................................... 36 3-1 Internal ROM Capacity .................................................................................................................................. 43 3-2 Vector Table .................................................................................................................................................. 43 3-3 Special-Function Registers ............................................................................................................................ 55 4-1 Port Functions ............................................................................................................................................... 65 4-2 Configuration of Port...................................................................................................................................... 66 4-3 Port Mode Registers and Output Latch Settings When Using Alternate Functions........................................ 73 5-1 Configuration of Clock Generator .................................................................................................................. 76 5-2 Maximum Time Required for Switching CPU Clock....................................................................................... 85 6-1 Operation Modes ...
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... Differences Between PD78F9468 and Mask ROM Versions ..................................................................... 180 15-2 Differences in LCD Controller/Driver of 15-3 Communication Mode List ........................................................................................................................... 183 15-4 Pin Connection List ...................................................................................................................................... 184 17-1 Operand Identifiers and Description Methods .............................................................................................. 190 20-1 Surface Mounting Type Soldering Conditions .............................................................................................. 212 20 LIST OF TABLES (2/2) Title µ PD78F9468 and Mask ROM Version........................................... 181 User’ ...
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Features • ROM and RAM capacities Item Part Number µ PD789462 Mask ROM µ PD789464 µ PD789466 µ PD789467 µ PD78F9468 Flash memory • Minimum instruction execution time can be changed from high-speed (0.4 system clock) to ultra-low-speed (122 ...
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Ordering Information Part Number µ PD789462GB-×××-8ET µ PD789464GB-×××-8ET µ PD789466GB-×××-8ET µ PD789467GB-×××-8ET µ PD78F9468GB-8ET ××× indicates ROM code suffix. Remark 22 CHAPTER 1 GENERAL Package 52-pin plastic LQFP (10 × 10) 52-pin plastic LQFP (10 × 10) 52-pin plastic ...
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... P42/KR02 P41/KR01 P40/KR00 P03 P02 P01 P00 INTP0/ANI0/P61 P11 P10 Caution Connect the IC0 (Internally Connected) pin directly to V Remark The parenthesized values apply to the CHAPTER 1 GENERAL µ PD789464GB-×××-8ET µ PD78F9468GB-8ET ...
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... ANI0: Analog input CAPH, CAPL: LCD power supply capacitance control COM0 to COM3: Common output IC0: Internally connected INTP0: External interrupt input KR00 to KR03: Key return P00 to P03: Port 0 P10, P11: Port 1 P40 to P43: Port 4 P60, P61: Port 6 P80 to P85: Port 8 24 ...
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Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Small-scale package, general-purpose applications µ 44-pin PD789046 µ 42-/44-pin PD789026 µ 30-pin PD789088 µ 30-pin PD789074 µ 28-pin PD789014 ...
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The major functional differences among the subseries are listed below. Series for General-Purpose Applications and LCD Drive Function ROM Capacity Subseries µ Small- PD789046 16 KB scale µ PD789026 package, µ PD789088 ...
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Series for ASSP Function ROM Capacity Subseries 8-Bit 16-Bit Watch WDT µ USB PD789800 µ Inverter PD789842 Note control µ On-chip PD789852 32KB ...
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Block Diagram 8-bit Cascaded timer 30 16-bit 8-bit timer TO40/P60 timer 40 Watch timer Watchdog timer ANI0/P61 A/D converter S0 to S16 S17/P85 to S22/P80 COM0 to COM3 LCD controller V LC0 driver V LC1 V LC2 CAPH CAPL ...
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Overview of Functions Part Number Item Internal memory ROM High-speed RAM LCD display RAM Main system clock (oscillation frequency) Subsystem clock (oscillation frequency) Minimum instruction execution time General-purpose registers Instruction set I/O ports Timers Timer outputs A/D converter LCD ...
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An outline of the timers is shown below. Operation Interval timer mode External event counter Function Timer output Square-wave output Capture Interrupt sources Notes 1. The watch timer can perform both watch timer and interval timer functions at the same ...
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List of Pin Functions (1) Port pins Pin Name I/O P00 to P03 I/O Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, the use of on-chip pull-up resistors can ...
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... LCD controller/driver segment signal outputs S17 to S22 COM0 to COM2 Output LCD controller/driver common signal outputs COM3 Output − CAPH, CAPL Voltage boost capacitor for LCD drive connection pins − LCD drive voltage LC0 LC2 X1 Input Connecting crystal resonator for main system clock oscillation − ...
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Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port and can be set to the input or output port mode in 1-bit units using port mode register 0 (PM0). When used ...
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... LC0 LC2 These pins are the power supply voltage pins for driving the LCD. 2.2.9 CATH, CAPL These pins are used to connect a voltage booster capacitor for driving the LCD. 2.2.10 RESET This pin inputs an active-low system reset signal. 2.2.11 X1, X2 These pins are used to connect a crystal resonator for main system clock oscillation. ...
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... IC0 (mask ROM version only) The IC0 (Internally Connected) pin is used to set the before shipment. In the normal operation mode, directly connect this pin to the V possible potential difference is generated between the IC0 pin and V noise superimposed on the IC0 pin, the user program may not run correctly. ...
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... Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the I/O circuit configuration of each type, see Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name I/O Circuit Type ...
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Type 5-A Pull-up enable V DD Data P-ch Output N-ch disable V SS Input enable Type 17-D V LC0 P-ch P-ch V LC1 N-ch SEG data P-ch V LC2 N-ch N- Type 18-B V LC0 P-ch P-ch V ...
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Memory Space The PD78467 Subseries can access memory space. Figures 3-1 to 3-5 show the memory maps. FFFFH Special-function registers FF00H FEFFH Internal high-speed RAM FE00H FDFFH FA17H FA16H Data FA00H memory space F9FFH 1000H 0FFFH ...
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Figure 3-2. Memory Map ( PD789464) FFFFH Special-function registers FF00H FEFFH Internal high-speed RAM FE00H FDFFH FA17H FA16H LCD display RAM Data FA00H memory space F9FFH 2000H 1FFFH Program memory space 0000H CHAPTER 3 CPU ARCHITECTURE 256 8 bits 256 ...
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FFFFH Special-function registers FF00H FEFFH Internal high-speed RAM FD00H FCFFH FA17H FA16H Data FA00H memory space F9FFH 4000H 3FFFH Program memory space 0000H 40 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( PD789466) 256 8 bits 512 8 bits ...
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Figure 3-4. Memory Map ( PD789467) FFFFH Special-function registers FF00H FEFFH Internal high-speed RAM FD00H FCFFH FA17H FA16H LCD display RAM Data FA00H memory space F9FFH 6000H 5FFFH Program memory space 0000H CHAPTER 3 CPU ARCHITECTURE 256 8 bits 512 ...
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FFFFH Special-function registers FF00H FEFFH Internal high-speed RAM FD00H FCFFH FA17H FA16H Data FA00H memory space F9FFH 8000H 7FFFH Program memory space 0000H 42 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( PD78F9468) 256 8 bits 512 8 bits ...
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Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD789467 Subseries provides internal ROM (or flash memory) with the following capacity for each ...
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Internal data memory (internal high-speed RAM) space PD789467 Subseries products incorporate the following RAM. (1) Internal high-speed RAM Internal high-speed RAM is incorporated in the area between FE00H and FEFFH in the PD789462 and 789464, and in the area ...
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Data memory addressing The PD789467 Subseries is provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area especially, specific addressing modes that correspond to the particular ...
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Figure 3-7. Data Memory Addressing ( PD789464) FFFFH Special-function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 256 8 bits FE20H FE1FH FE00H FDFFH Reserved FA17H FA16H LCD display RAM 23 4 bits FA00H F9FFH Reserved ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( PD789466) FFFFH Special-function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 512 8 bits FE20H FE1FH FD00H FCFFH Reserved FA17H FA16H LCD display RAM 23 4 ...
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Figure 3-9. Data Memory Addressing ( PD789467) FFFFH Special-function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 512 8 bits FE20H FE1FH FD00H FCFFH Reserved FA17H FA16H LCD display RAM 23 4 bits FA00H F9FFH Reserved ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( PD78F9468) FFFFH Special-function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH Internal high-speed RAM 512 8 bits FE20H FE1FH FD00H FCFFH Reserved FA17H FA16H LCD display RAM 23 4 ...
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Processor Registers The PD789467 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are ...
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CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgment operations of the CPU. When set to the interrupt disabled status (DI), and interrupt requests other than non-maskable interrupt are all ...
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Stack pointer (SP) This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high- speed RAM area can be set as the stack area. Figure 3-13. Stack Pointer Configuration 15 ...
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General-purpose registers The general-purpose registers consist of eight 8-bit registers ( and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a ...
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Special-function registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. The special-function registers are allocated in the 256-byte area of FF00H to FFFFH. Special-function registers can be manipulated, like general-purpose registers, by operation, transfer, and ...
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Address Special-Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF03H port 4 FF05H Port 6 FF08H Port 8 FF15H A/D conversion result register FF20H Port mode register 0 FF21H Port mode register 1 FF24H Port mode register 4 ...
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Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. The CALL !addr16 and BR !addr16 ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) ...
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Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal ...
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Special-function register (SFR) addressing [Function] The memory-mapped special-function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH ...
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Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out ...
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Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code ...
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Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as ...
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Port Functions µ The PD789467 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on ...
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... This is a 4-bit I/O port with an output latch. Port 0 can be set to the input or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units using pull-up resistor option register 0 (PU0). Port 0 is set in the input mode when the RESET signal is input. ...
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... This is a 2-bit I/O port with an output latch. Port 1 can be set to the input or output mode in 1-bit units using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units using pull-up resistor option register 0 (PU0). This port is set in the input mode when the RESET signal is input. ...
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... This is a 4-bit I/O port with an output latch. Port 4 can be set to the input or output mode in 1-bit units using port mode register 4 (PM4). When using the P40 to P43 pins as input port pins, on-chip pull-up resistors can be connected in 4-bit units using pull-up resistor option register 0 (PU0). ...
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Port 6 This is a 2-bit I/O port with an output latch. Port 6 can be set to the input or output mode in 1-bit units using port mode register 6 (PM6). This port is also used as a ...
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A/D converter – WR ADS0 ADS00 External interrupt RD WR PORT Output latch (P61 PM61 ADS0: A/D input selection register 0 PM: Port mode register RD: Port 6 read signal WR: Port 6 write signal 70 CHAPTER ...
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Port 8 This is a 6-bit input port. This port is also used as a segment output, and can be switched to the port function or segment output function in 1-bit units using port function register 8 (PF8). This ...
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Registers Controlling Port Function The ports are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM4, PM6) • Pull-up resistor option register 0 (PU0) • Port function register 8 (PF8) (1) Port mode ...
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Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions Pin Name P40 to P43 KR00 to KR03 P60 TO40 P61 INTP0 ANI0 ×: Remark Don’t care PM××: Port mode register P××: Port output latch ADS00: Bit ...
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... Cautions 1. Bits 6 and 7 must be set When any one of pins P80 to P85 is used as a general-purpose pin, observe the following two restrictions (because an ESD protection circuit for the LCD pins is connected to the V • Enable operation of the booster (VAON0 = 1). • 3.0 V mode (GAIN = 1)... Use the microcontroller in the range of V LC0 3 ...
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Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written ...
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Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • Main system clock (ceramic/crystal) oscillator This circuit oscillates at 1.0 ...
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Figure 5-1. Block Diagram of Clock Generator Internal bus Suboscillation mode register FRC SCC Subsystem XT1 f XT clock XT2 oscillator X1 Main system f X clock X2 oscillator STOP MCC PCC1 Processor clock control register (PCC) CHAPTER 5 CLOCK ...
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Registers Controlling Clock Generator The clock generator is controlled by the following three registers. • Processor clock control register (PCC) • Suboscillation mode register (SCKM) • Subclock control register (CSS) (1) Processor clock control register (PCC) PCC sets CPU ...
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... Operation enabled 1 Operation disabled Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. When the subclock is not used, the current consumption in STOP mode can be further reduced by setting FRC = 1. Caution Bits must be set to 0. ...
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... System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin ...
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... Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the inverted signal to the XT2 pin. ...
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... (c) Wiring near high fluctuating current Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series. 82 CHAPTER 5 CLOCK GENERATOR X2 (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) X2 ...
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... Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to XT2 in series. Caution If the X1 wire is in parallel with the XT2 wire, crosstalk noise may occur between X1 and XT2, resulting in a malfunction. To avoid this, do not lay the X1 and XT2 wires in parallel. ...
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Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • Main system clock f X • Subsystem clock f XT • CPU clock f CPU ...
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Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit ...
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Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 5-8. Example of Switching Between System Clock and CPU Clock V DD RESET Input request signal System clock CPU ...
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... Interval timer with 8-bit resolution • Square-wave output with 8-bit resolution (timer 40 only) (2) 16-bit timer counter mode (cascade connection mode) Operation as a 16-bit timer is enabled during cascade connection mode. The following functions can be used in this mode. • Interval timer with 16-bit resolution • ...
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Configuration of 8-Bit Timers 30 and 40 The 8-bit timers 30 and 40 include the following hardware. Table 6-2. Configuration of 8-Bit Timers 30 and 40 Item 8 bits × 2 (TM30, TM40) Timer counters Compare registers: 8 bits ...
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... Decoder (CR30) Selector 8-bit timer counter 30 (TM30) Clear Selector Cascade connection mode (E) From Figure 6-2 (E) Timer 40 match signal (in cascade connection mode) To Figure 6-2 (G) Match (G) Timer 30 match signal (in carrier generator mode) OVF Internal reset signal INTTM30 (F) To Figure 6-2 (F) Timer 30 match signal (in cascade connection mode) ...
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... RMC40 NRZB40 NRZ40 From Figure 6-1 (G) Timer counter match signal from (G) timer 30 (in carrier generator mode) TO40/P60 Note To Figure 6-1 (C) Carrier clock (C) To Figure 6-1 (A) Bit 7 of TM40 (A) (in cascade connection mode) Internal reset signal INTTM40 To Figure 6-1 (B) Timer 40 interrupt request signal (B) count clock input signal to TM30 ...
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... When connected to TM30 via a cascade connection and used as a 16-bit timer, the interrupt request (INTTM40) occurs only when matches occur simultaneously between CR30 and TM30 and between CR40 and TM40 (INTTM30 does not occur) ...
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... When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0 • When a match occurs between TM40 and CR40 • When the TM40 count value overflows (b) Cascade connection mode (TM30 and TM40 are simultaneously cleared to 00H) • After reset • When the TCE40 flag is cleared to 0 • ...
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Registers Controlling 8-Bit Timers 30 and 40 8-bit timer 30 and 40 are controlled by the following five registers. • 8-bit timer mode control register 30 (TMC30) • 8-bit timer mode control register 40 (TMC40) • Carrier generator output ...
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... Other than above Notes 1. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode, any setting for TCE30 is ignored. 2. The operation mode selection is set to both the TMC30 register and TMC40 register. Cautions 1. In cascade connection mode, the timer 40 output signal is forcibly selected for the count clock ...
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... Output disabled (port mode) 1 Output enabled Notes 1. Since the count operation is controlled by TCE40 in cascade connection mode, any setting for TCE30 (bit 7 of TMC30) is ignored. 2. The operation mode selection is set to both the TMC30 register and TMC40 register. Caution Be sure to clear bit ...
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... When NRZ40 = 1, high-level signal is output to TO40/P60 pin NRZB40 This is the bit that stores the next data to be output to NRZ40. Data is transferred to NRZ40 at the rising edge of the timer 30 match signal. Input the necessary value in NRZB40 in advance by program. NRZ40 0 Output low-level signal (carrier clock is stopped) ...
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Port mode register 6 (PM6) This register is used to set the I/O mode of port 6 in 1-bit units. When using the P60/TO40 pin as a timer output, set the PM60 and P60 output latch to 0. PM6 ...
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Operation of 8-Bit Timers 30 and 40 6.4.1 Operation as 8-bit timer counter Timers 30 and 40 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counters. • Interval timer ...
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Table 6-3. Interval Time of Timer 30 (at f TCL301 TCL300 Minimum Interval Time (12 (51 Input cycle of timer 40 match signal 1 1 Carrier ...
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Figure 6-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H) Count clock TMn0 CRn0 TCEn0 Count start INTTMn0 TOn0 Remark Figure 6-10. Timing of Interval Timer Operation with 8-Bit Resolution ...
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Figure 6-11. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from < M)) Count clock N 00H 01H TMn0 N CRn0 TCEn0 Count start INTTMn0 TOn0 Remark Figure 6-12. ...
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Figure 6-13. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock) Timer 40 count clock 00H 01H TM40 N CR40 TCE40 Count start INTTM40 Input clock to timer 30 ...
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Operation as square-wave output with 8-bit resolution (timer 40 only) Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register 40 (CR40). To operate timer 40 for square-wave output, ...
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Figure 6-14. Timing of Square-Wave Output with 8-Bit Resolution t Count clock 00H 01H TM40 CR40 TCE40 Count start INTTM40 Note TO40 Note The initial value of TO40 is low level when output is enabled (TOE40 = 1). Square-wave output ...
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... Operation as 16-bit timer counter Timers 30 and 40 can be used as 16-bit timer counters via a cascade connection. In this case, 8-bit timer counter 30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls reset and clear. The following modes can be used for the 16-bit timer counter. ...
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Figure 6-15. Timing of Interval Timer Operation with 16-Bit Resolution t TM40 count clock TM40 count value 00H N 7FH 80H Not cleared because TM30 does not match CR40 TCE40 Count start TM30 count clock TM30 00H ...
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Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and CR40. To operate as a square-wave output with 16-bit resolution, settings must ...
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Figure 6-16. Timing of Square-Wave Output with 16-Bit Resolution t TM40 count clock TM40 count clock 00H N 7FH 80H Not cleared because TM30 does not match CR40 TCE40 Count start TM30 count clock TM30 00H X ...
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... Be sure to use an 8-bit memory manipulation instruction enable operation in the carrier generator mode, set a value to the compare registers (CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in advance. Otherwise, the signal of the timer match circuit will become unstable and the NRZ40 flag will be undefined ...
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Figures 6-17 to 6-19 show the operation timing of the carrier generator. Figure 6-17. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N)) TM40 count clock TM40 00H 01H N count value CR40 N ...
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Figure 6-18. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N)) TM40 count clock TM40 00H M count value CR40 N CRH40 M TCE40 Count start INTTM40 Carrier clock TM30 count clock 01H X ...
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Figure 6-19. Timing of Carrier Generator Operation (When CR40 = CRH40 = N) TM40 count clock TM40 00H N 00H count value Clear CR40 N CRH40 N TCE40 Count start INTTM40 Carrier clock TM30 count clock 00H 01H X TM30 ...
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Operation as PWM output (timer 40 only) In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a high-level width using CRH40. To operate timer 40 in ...
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Figure 6-20. PWM Output Mode Timing (Basic Operation) TM40 count clock TM40 01H 00H N count value CR40 N CRH40 M TCE40 Count start INTTM40 Note TO40 Note The initial value of TO40 is low level when output is enabled ...
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Notes on Using 8-Bit Timers 30 and 40 (1) Error on starting timer An error 1.5 clocks is included in the time between when the timer is started and a match signal is generated. This is ...
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Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 7-1 shows a block diagram of the watch timer. Figure ...
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Watch timer The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to generate an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used ...
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Register Controlling Watch Timer The watch timer mode control register (WTM) is used to control the watch timer. • Watch timer mode control register (WTM) WTM selects the count clock for the watch timer and specifies whether to enable ...
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Watch Timer Operation 7.4.1 Operation as watch timer The watch timer is used to generate an interrupt request at 0.5-second intervals using the main system clock (4.19 MHz) or subsystem clock (32.768 kHz). By setting bits 0 and 1 ...
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Figure 7-3. Watch Timer/Interval Timer Operation Timing 5-bit counter 0H Start Count clock Watch timer interrupt INTWT Watch timer interrupt time (0.5 s) Interval timer interrupt INTWTI Caution When operation of the watch timer and 5-bit ...
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Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select either the watchdog timer mode or interval timer mode using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog ...
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Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 8-3. Configuration of Watchdog Timer Item Control registers Watchdog timer clock selection register (TCL2) Watchdog timer mode register (WDTM) Figure 8-1. Block Diagram of Watchdog Timer f X ...
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Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer clock selection register (TCL2) • Watchdog timer mode register (WDTM) (1) Watchdog timer clock selection register (TCL2) This register sets the watchdog ...
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Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. ...
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Watchdog Timer Operation 8.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (program loop detection time interval) ...
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Operation as interval timer When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt ...
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CHAPTER 9 8-BIT A/D CONVERTER 9.1 Functions of 8-Bit A/D Converter The 8-bit A/D converter is an 8-bit resolution converter that converts analog inputs to digital signals. This converter can control one channel of analog inputs (ANI0). A/D conversion can ...
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Figure 9-1. Block Diagram of 8-Bit A/D Converter ANI0/INTP0/P61 ADS00 A/D input selection register 0 (ADS0) (1) Successive approximation register (SAR) The SAR receives the result of comparing an analog input voltage and a voltage at the voltage tap (comparison ...
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CHAPTER 9 8-BIT A/D CONVERTER (5) Series resistor string The series resistor string is configured between V which analog inputs are compared. (6) ANI0 pin The ANI0 pin is the 1-channel analog input pin for the A/D converter ...
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Registers Controlling 8-Bit A/D Converter The following two registers are used to control the 8-bit A/D converter. • A/D converter mode register 0 (ADM0) • A/D input selection register 0 (ADS0) (1) A/D converter mode register 0 (ADM0) ADM0 ...
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A/D input selection register 0 (ADS0) The ADS0 register specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ...
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A/D Converter Operation 9.4.1 Basic operation of 8-bit A/D converter <1> Set bit 0 of A/D input selection register 0 (ADS0) so that the P61/INTP0/ANI0 pin can be used as an analog input. <2> The analog input voltage ...
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A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the A/D ...
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Operation mode of 8-bit A/D converter A/D input selection register 0 (ADS0) is used to select the function of the P61/INTP0/ANI0 pin to be used as an analog input for A/D conversion. A/D conversion can only be started by ...
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Cautions Related to 8-Bit A/D Converter (1) Current consumption in standby mode When the A/D converter enters a standby mode, it stops operating. Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0 can reduce the ...
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Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D converter operation is undefined. Be sure to poll the A/D conversion end interrupt request (INTAD0), discard the first conversion result ...
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CHAPTER 9 8-BIT A/D CONVERTER (6) Noise prevention To maintain a resolution of 8 bits, watch for noise at the V impedance of the analog input source, the larger the effect by noise. To reduce noise, attach an external capacitor ...
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... ADCR0 INTAD0 (10) Input impedance of V pin DD A series resistor string of several 10 kΩ is connected across the V Therefore, if the output impedance of the reference voltage source is high, this high impedance is eventually connected in series with the series resistor string across the V voltage error. 138 ...
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CHAPTER 10 LCD CONTROLLER/DRIVER 10.1 Functions of LCD Controller/Driver The features of the LCD controller/driver of the (1) Automatic output of segment and common signals based on automatic display data memory read (2) Four different frame frequencies selectable (3) Up ...
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LCD clock control LCD display mode register 0 register 0 LCDC03 LCDC02 LCDC01 LCDC00 LCDON0 LCD X Prescaler LCD LCD ...
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Registers Controlling LCD Controller/Driver • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) • LCD voltage boost control register 0 (LCDVA0) • Port function register 8 (PF8) (1) LCD display mode register 0 (LCDM0) ...
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Cautions 1. Bits and 5 must be set When the main system clock is selected as the LCD source clock, if the STOP mode is selected, an abnormal display may occur. Before selecting the ...
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... LCDC03 LCDC02 LCDC01 LCD source clock (f LCD LCD clock (LCDCL) selection ) frequency of at least 32 kHz. LCD = 5.0 MHz (32.768 kHz) is connected to the LCD source clock (f XT Table 10-3. Frame Frequencies (Hz (64 Hz) (128 Hz User’s Manual U15552EJ2V1UD < ...
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LCD voltage boost control register 0 (LCDVA0) LCDVA0 controls the voltage boost level during the voltage boost operation. LCDVA0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDVA0 to 00H. Figure 10-4. Format of ...
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Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. Before changing the LCD clock or voltage boost level, disable display and voltage boost. 10.4.1 Setting before starting display <1> With the default setting after reset, select the ...
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LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA16H. Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller/driver. Figure 10-6 shows the relationship ...
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Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, V difference becomes lower than V . ...
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Figure 10-7 shows the common signal waveforms, and Figure 10-8 shows the voltages and phases of the common and segment signals. Figure 10-7. Common Signal Waveforms COMn (Four-time-slice mode One LCD clock cycle Figure 10-8. Voltages and ...
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... FA00H to FA15H) correspond to this display. The following description focuses on numeral “6.” the LCD panel necessary to apply the select or deselect voltage to the S12 and S13 pins according to Table 10-5 at the timing of the common signals COM0 to COM3. Table 10-5. Select and Deselect Voltages (COM0 to COM3) According to Table 10- determined that the display data memory location (FA0CH) that corresponds to S12 must contain 1101 ...
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... Figure 10-10. Example of Connecting Four-Time-Slice LCD Panel FA00H FA10H 150 CHAPTER 10 LCD CONTROLLER/DRIVER COM 3 COM 2 COM 1 COM ...
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CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-11. Examples of Four-Time-Slice LCD Drive Waveform COM0 COM1 COM2 COM3 S12 COM0-S12 COM1-S12 Remark The waveforms of COM2-S12 and COM3-S12 are not shown above User’s Manual U15552EJ2V1UD V LC0 V LC1 V ...
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... Figure 10-12 for connection. 2. The power for the LCD drive is supplied separately from the therefore, a constant voltage can be supplied regardless of the change of V Figure 10-12. Example of Pin Connection for LCD Driver Remark Use capacitors with as little leakage as possible. Use a non-polar capacitor for C1. 152 ...
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CHAPTER 11 POWER-ON-CLEAR CIRCUIT µ The PD789467 Subseries provides a power-on-clear (POC) circuit. In the flash memory version ( the POC circuit is always operating. However, it can only be used when selected by a mask option in mask ROM ...
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CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.3 Power-on-Clear Circuit Operation The POC circuit compares the detection voltage (V internal reset signal if V < POC Figure 11-2. Timing of Internal Reset Signal Generation of POC Circuit Power supply voltage ...
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CHAPTER 12 INTERRUPT FUNCTION 12.1 Interrupt Types The following two types of interrupts are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. ...
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Note 1 Interrupt Type Priority Name − Non-maskable INTWDT Maskable 0 INTWDT 1 INTP0 2 INTAD0 3 INTWT 4 INTTM30 5 INTTM40 6 INTKR00 7 INTWTI Notes 1. “Priority” is the priority order when more than one maskable interrupt request ...
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CHAPTER 12 INTERRUPT FUNCTION Figure 12-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Interrupt request (B) Internal maskable interrupt MK Interrupt request IF (C) External maskable interrupt INTM0, KRM00 Interrupt Edge request detector INTP0: External interrupt mode register ...
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Registers Controlling Interrupt Function The following five registers are used to control the interrupt function. • Interrupt request flag register 0 (IF0) • Interrupt mask flag register 0 (MK0) • External interrupt mode register 0 (INTM0) • Program status ...
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Interrupt request flag register 0 (IF0) An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed cleared (0) when the interrupt request is acknowledged, when the RESET ...
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External interrupt mode register 0 (INTM0) INTM0 is used to specify the valid edge for INTP0. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. Figure 12-4. Format of External Interrupt Mode Register ...
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... KRM00, clear KRMK00 after clearing bit 6 of IF0 (KRIF00 = 0) to enable interrupts. 3. On-chip pull-up resistors are automatically connected in input mode to the pins specified for key return signal detection (P40 to P43). Although these resistors are disconnected when the mode changes to output, rising edge detection continues unchanged ...
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Interrupt Servicing Operation 12.4.1 Non-maskable interrupt request acknowledgment operation A non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled not subject to interrupt priority control and takes precedence over all other interrupts. When a non-maskable ...
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Figure 12-8. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment (watchdog timer mode (non-maskable interrupt Interrupt request is generated Interrupt servicing starts WDTM: Watchdog timer mode register WDT: Figure 12-9. Timing of Non-Maskable Interrupt Request Acknowledgment CPU processing Instruction ...
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Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared vectored interrupt request is acknowledged in the ...
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Figure 12-12. Interrupt Request Acknowledgment Timing (Example: MOV A, r) Clock MOV A, r CPU Interrupt If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under execution, n clocks ( ...
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Figure 12-14. Example of Multiple Interrupt Servicing Example 1. Acknowledging multiple interrupts Main servicing INTxx The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupt servicing is performed. Before each interrupt ...
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Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is ...
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Standby Function and Configuration 13.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. (1) HALT mode This mode is set when the HALT ...
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Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time selection register (OSTS). OSTS is set with an 8-bit or 1-bit memory manipulation ...
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Standby Function Operation 13.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation statuses in the HALT mode are shown in the following table. Table 13-1. Operation Statuses in HALT Mode ...
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Releasing HALT mode The HALT mode can be released by the following three sources. (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be ...
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Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 13-3. Releasing HALT ...
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STOP mode (1) STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon set ...
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Releasing STOP mode The STOP mode can be released by the following two sources. (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to ...
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Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 13-5. Releasing STOP Mode by RESET Input STOP instruction RESET signal Operation ...
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The following three operations are available to generate reset signals. (1) External reset signal input via RESET pin (2) Internal reset by detection of watchdog timer program loop time (3) Internal reset using power-on-clear circuit (POC) The external and internal ...
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Figure 14-2. Reset Timing by RESET Input X1 During normal operation RESET Internal reset signal Port pin Figure 14-3. Reset Timing by Overflow in Watchdog Timer X1 During normal operation Overflow in watchdog timer Internal reset signal Port pin Figure ...
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Figure 14-5. Reset Timing by Power-on Clear (a) At power application X1 Reset period (oscillation stops Internal reset signal Port pin (b) In STOP mode X1 STOP instruction execution Normal operation V DD Power-on-clear voltage (V Internal reset ...
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Table 14-1. Hardware Status After Reset Note 1 Program counter (PC) Stack pointer (SP) Program status word (PSW) RAM Data memory General-purpose registers Ports (P0, P1, P4, P6) (output latches) Port mode registers (PM0, PM1, PM4, PM6) Port function register ...
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The PD78F9468 is available as the flash memory version of the µ The PD78F9468 is a version with the internal ROM of the flash memory. The differences between the Table 15-1. Differences Between Part Number Flash Memory Version µ ...
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The PD78F9468 and mask ROM version differ in the on-chip LCD controller/driver macro. The differences in the µ LCD controller/driver of PD78F9468 and mask ROM version is shown in Table 15-2. Table 15-2. Differences in LCD Controller/Driver of Item ...
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... Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the target system (on-board write). A flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided ...
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Communication mode Use the communication mode shown in Table 15-3 to perform communication between the dedicated flash µ programmer and PD78F9468. Communication Mode COMM PORT SIO Clock 3-wire serial SIO ch-0 100 Hz to 1.25 Note2 I/O (3-wire, sync) ...
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... Figure 15-3. Example of Connection with Dedicated Flash Programmer Dedicated flash programmer Note Connect this pin when the system clock is supplied by the dedicated flash programmer oscillator is already connected to the X1 pin, do not connect X1 to the CLK pin. Caution The V pin, if already connected to the power supply, must be connected to the VDD pin of the DD dedicated flash programmer ...
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... On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. <V pin> normal operation mode, input the V V (TYP ...
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... Abnormal operation of other device If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the signals input to the other device are ignored ...
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... If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed ...
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... Connection on flash memory writing adapter The following shows an example of the recommended connection when using the flash memory writing adapter. Figure 15-8. Wiring Example of Flash Memory Writing Adapter Using 3-Wire Serial I/O Mode 188 µ CHAPTER 15 PD78F9468 ...
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The mask ROM versions ( PD789462, 789464, 789466, and 789467) have the following mask option. • Power-on-clear (POC) circuit Use/non use of the POC circuit can be selected. <1> POC circuit used <2> POC circuit not used Caution The ...
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This chapter lists the instruction set of the language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 17.1 Operation 17.1.1 Operand identifiers and description methods Operands are described in the “Operands” column of each instruction ...
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Description of “Operation” column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register ...
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Operation List Mnemonic Operands MOV r, #byte saddr, #byte sfr, #byte saddr saddr sfr sfr !addr16 !addr16, A PSW, #byte A, PSW PSW [DE] [DE [HL] ...
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Mnemonic Operands MOVW rp, #word AX, saddrp saddrp, AX AX, rp rp, AX XCHW AX, rp ADD A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL+byte] ADDC A, #byte saddr, #byte saddr ...
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Mnemonic Operands SUBC A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL+byte] AND A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL+byte #byte saddr, #byte ...
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Mnemonic Operands CMP A, #byte saddr, #byte saddr A, !addr16 A, [HL] A, [HL+byte] ADDW AX, #word SUBW AX, #word CMPW AX, #word INC r saddr DEC r saddr INCW rp DECW rp ROR A, 1 ROL ...
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Mnemonic Operands CALL !addr16 CALLT [addr5] RET RETI PUSH PSW rp POP PSW rp MOVW SP !addr16 $addr16 AX BC $saddr16 BNC $saddr16 BZ $saddr16 BNZ $saddr16 BT saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 ...
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Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r 1st Operand ADD MOV Note A ADDC ...
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MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word 1st Operand AX ADDW SUBW CMPW rp MOVW saddrp SP Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, ...
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Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand 1st Operand Basic Instructions Compound Instructions (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP CHAPTER 17 INSTRUCTION SET AX !addr16 [addr5] BR CALL CALLT ...
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CHAPTER 18 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A Parameter Symbol Supply voltage V V Input voltage Output voltage V V Output current, high Output current, low Operating ambient temperature Storage temperature T Notes 1. Make sure that the following ...