RM7000A-350T PMC-Sierra Inc, RM7000A-350T Datasheet
RM7000A-350T
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RM7000A-350T Summary of contents
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... RM7000A™ Microprocessor with On- Chip Secondary Cache Proprietary and Confidential Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet RM7000A Data Sheet Released Issue 2, May 2001 ...
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... PMC-Sierra, Inc. has been advised of the possibility of such damage. Trademarks RM7000A and Fast Packet Cache are trademarks of PMC-Sierra, Inc. Patents The technology discussed is protected by one or more of the following Patents. U.S. Patent Numbers 5,953,748, 5,953,748, 5,953,748 Relevant patent applications and other patents may also exist ...
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... Issue Date 2 May 2001 1 January 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers' Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet ECN Number Originator Details of Change 3716 K. Murray Changed pin AC13 SysCmd[2] from active low to high ...
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... All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold typeface. All instruction names, such as MFHI, are in san serif typeface. • Proprietary and Confidential to PMC-Sierra, Inc and for its Customers' Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Released 4 ...
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... Cache Management .....................................................................................................27 4.24 Primary Write Buffer .....................................................................................................27 4.25 System Interface ..........................................................................................................27 4.26 System Address/Data Bus ...........................................................................................28 4.27 System Command Bus ................................................................................................28 4.28 Handshake Signals ......................................................................................................29 4.29 System Interface Operation .........................................................................................29 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers' Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Released 5 ...
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... Boot-Time Interface Parameters ..................................................................................48 11 Timing Diagrams ...................................................................................................................49 11.1 Clock Timing ................................................................................................................49 12 Packaging Information ..........................................................................................................50 13 RM7000A Pinout ...................................................................................................................51 14 Ordering Information .............................................................................................................53 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Released 6 ...
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... Figure 11 Multiple Outstanding Reads ......................................................................................31 Figure 12 Clock Timing ..............................................................................................................49 Figure 13 Input Timing ...............................................................................................................49 Figure 14 Output Timing ............................................................................................................49 Figure 15 304 TBGA Drawing ...................................................................................................50 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Released 7 ...
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... Table 18 Clock/Control Interface ...............................................................................................40 Table 19 Tertiary Cache Interface .............................................................................................41 Table 20 Interrupt Interface .......................................................................................................42 Table 21 JTAG Interface ...........................................................................................................42 Table 22 Initialization Interface ..................................................................................................42 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Released 8 ...
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... Fully static CMOS design with dynamic power down logic • RM5271 pin compatible, 304 pin TBGA package, 31x31 mm Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Released 9 ...
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... Cvt, Div, Sqrt Multiplier Array Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Extenal Cache Controller On-chip 256K Byte Secondary Cache, 4-way Set Associative Secondary Tags ...
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... It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. The RM7000A integrates 16 KB 4-way set associative instruction and data caches along with an integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are write-back and non-blocking ...
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... Superscalar Dispatch The RM7000A incorporates a superscalar dispatch unit that allows it to issue up to two instructions per cycle. For purposes of instruction issue, the RM7000A defines four classes of instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the function pipeline and the memory pipeline. Note however that the M pipe can execute integer as well as memory type instructions ...
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... W, pipe stage. The physical length of the floating-point execution pipeline is actually seven stages but this is completely transparent to the user. Figure 4 shows instruction execution within the RM7000A when instructions are issuing simultaneously down both pipelines. As illustrated in the figure ten instructions can be executing simultaneously ...
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... Register File The RM7000A has thirty-two general purpose registers with register location 0 (r0) hard wired to a zero value. These registers are used for scalar integer operations and address calculation. In order ...
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... ALU The RM7000A has two complete integer ALUs each consisting of an integer adder/subtractor, a logic unit, and a shifter. Table 3 shows the functions performed by the ALUs for each execution unit. Each of these units is optimized to perform all operations in a single processor cycle. Table 3 ALU Operations ...
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... The floating-point coprocessor is a tightly coupled execution unit, decoding and executing instructions in parallel with, and in the case of floating-point loads and stores, in cooperation with the M pipe of the integer unit. The superscalar capabilities of the RM7000A allow floating-point computation instructions to issue concurrently with integer instructions. ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Repeat Rate single/double 4 ...
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... MFC0 and MTC0 instructions, the RM7000A supports the same registers as found in the RM5200 Family. In the control space, which is accessed by the previously unused CTC0 and CFC0 instructions, the RM7000A supports five new registers. The first three of these new 32-bit registers support the enhanced interrupt handling capabilities; Interrupt Control, Interrupt Priority Level Lo (IPLLO), and Interrupt Priority Level Hi (IPLHI) ...
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... The RM7000A processor also supports a supervisor mode in which the virtual address space is 256 32-bit mode), divided into three regions based on the high-order bits of the virtual address. Figure 6 shows the address space layout for 32-bit operations. ...
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... TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM7000A provides a random replacement algorithm to select a TLB entry to be written with a new mapping. However, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’ ...
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... Note that both of the write-through protocols bypass both the secondary and the tertiary caches since neither of these caches support writes of less than a complete cache line. These protocols are used for both code and data on the RM7000A with data using write-back or write-through depending on the application. The write-through modes support the same efficient frame buffer handling as the RM5200 Family ...
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... The RM7000A supports cache locking on a per line basis. The contents of each line of the cache can be locked by setting a bit in the Tag RAM. Locking the line prevents its contents from being overwritten by a subsequent cache miss ...
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... If the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). The store buffer allows the RM7000A to execute a store every processor cycle and to perform back-to-back stores without penalty. In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred ...
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... The RM7000A allows entries to be stored in the primary caches that do not necessarily have a corresponding entry in the secondary; the RM7000A does not force the primaries subset of the secondary. For example, if primary cache line A is being filled and a cache line already exists in the secondary for primary cache line B at the location where primary A’ ...
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... Tertiary Cache The RM7000A has direct support for an external tertiary cache. The tertiary cache is direct mapped and block write-through with byte parity protection for data. The RM7000A tertiary cache operates identical to the secondary cache of the RM527x while supporting additional size increments to support 4 MB and 8 MB caches. ...
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... Cache Locking The RM7000A allows critical code or data fragments to be locked into the primary and secondary caches. The user has complete control over the locking function. For instruction and data fragments in the primary caches, locking is accomplished by setting either or both of the cache lock enable bits and specifying the set in the CP0 ECC register, then executing either a load instruction for data Fill_I cache operation for instructions ...
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... System Interface The RM7000A provides a high-performance 64-bit system interface which is compatible with the RM5200 Family enhancement to the SysAD bus interface, the RM7000A allows half- Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ ...
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... System Address/Data Bus The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RM7000A and the rest of the system protected with an 8-bit parity check bus, SysADC[7:0]. The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies ...
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... Handshake Signals There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are driven by an external device to indicate to the RM7000A whether it can accept a new read or write transaction. The RM7000A samples these signals before deasserting the address on read and write requests ...
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... For processor reads, the RM7000A asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses. If the system interface has RdRdy* asserted, then the processor tristates its drivers and releases the system interface to slave state by asserting Release*. The external device can then begin sending data to the RM7000A. ...
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... PAck* TcMatch 4.30 Data Prefetch The RM7000A is the first PMC-Sierra design to support the MIPS IV integer data prefetch ( PREF ) and floating-point data prefetch ( PREFX ) instructions. These instructions are used by the compiler assembly language programmer when it is known or suspected that an upcoming data reference is going to miss in the cache. By appropriately placing a prefetch instruction, the memory latency can be hidden under the execution of other instructions ...
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... WrRdy*. 4.32 External Requests The RM7000A can respond to certain requests issued by an external device. These requests take one of two forms: Write requests and Null requests. An external device executes a write request when it wishes to update one of the processors writable resources such as the internal interrupt register ...
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... Watch exception. 4.34 Performance Counters To facilitate system tuning, the RM7000A implements a performance counter using two new CP0 registers, PerfCount and PerfControl. The PerfCount register is a 32-bit writable counter which causes an interrupt when bit 31 is set. The PerfControl register is a 32-bit register containing a 5- bit field which selects one of twenty-two event types as well as a handful of bits which control the overall counting function ...
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... The performance counter interrupt only occurs when interrupts are enabled in the Status register, IE=1, and the Interrupt Mask bit 13 (IM[13]) of the coprocessor 0 interrupt control register is set. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Released 34 ...
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... When a hang occurs the interrupt ultimately triggers, thereby breaking free from the hang-up. 4.35 Interrupt Handling In order to provide better real time interrupt handling, the RM7000A provides an extended set of hardware interrupts, each of which can be separately prioritized and separately vectored. In addition to the standard six external interrupt pins, the RM7000A provides four more interrupt pins for a total of ten external interrupts ...
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... Table 13 and Table 14 above. The priority level registers are located in the coprocessor 0 control register space. In addition to programmable priority levels, the RM7000A also permits the spacing between interrupt vectors to be programmed. For example, the minimum spacing between two adjacent vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set up the vectors as jumps to the actual interrupt routines or, if interrupt latency is paramount, to include the entire interrupt routine at one vector ...
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... Standby Mode The RM7000A provides a means to reduce the amount of power consumed by the internal core when the CPU is not performing any useful operations. This state is known as Standby Mode. Executing the WAIT instruction enables interrupts and causes the processor to enter Standby Mode ...
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... Dual-cycle deselect (DCD) 1: Single-cycle deselect (SCD) Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Mode bit Description 17:16 System configuration identifiers - software visible in processor Config[21..20] register ...
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... Input RdType Output Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Description External request Signals that the system interface is submitting an external request. Release interface Signals that the processor is releasing the system interface to slave ...
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... System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. System Command/Data Identifier Bus Parity For the RM7000A, unused on input and zero on output. Description System clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock ...
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... Input/Output Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Description Tertiary Cache Block Clear Requests that all valid bits be cleared in the Tag RAMs. Many RAMs may not support a block clear therefore the block clear capability is not required for the cache to operate ...
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... Allows the system to change the processor addressing mode without rewriting the mode ROM. Vcc is OK When asserted, this signal indicates to the RM7000A that the VccInt power supply has been above the recommended value for more than 100 milliseconds and will remain stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet 1 Limits –0 +85 – ...
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... Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the RM7000A Family Users Manual, Appendix E. 4. VccP must be connected to VccInt through a passive filter circuit. See RM7000 Family User’s Manual for recommended circuit. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’ ...
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... -0. 1. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Maximum Conditions 0.2V |I OUT 0.4V |I OUT 0.8V VccIO + 0. Maximum Conditions ...
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... Dhrystone 2.1 instruction mix. 3. I/O supply power is application dependant, but typically <20% of VccInt. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet CPU Speed 300 MHz 350 MHz 400 MHz 1 ...
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... JTAG Clock t JTAGCKP Period Note: Operation of the RM7000A is only guaranteed with the Phase Lock Loop Enabled. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Min ...
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... Mode Data Setup t DS Mode Data Hold t DH Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet CPU Speed 300 MHz Min Max Min 5,6 1.0 4.5 mode14.. (fastest) 1 ...
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... System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.) Figure 13 Input Timing SysClock Data Figure 14 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet t t High Low t t Fall Rise t t ...
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... All dimensions in millimeters unless otherwise indicated. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet E1, N ...
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... K20 SysAD[25] L1 SysAD[10] L20 Vcclnt M1 VsslO M20 VcclO Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Pin Function Pin A2 VssIO A3 A6 VsslO A7 A10 SysADC[1] A11 ...
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... RdType AC8 VsslO AC12 VsslO AC16 VsslO AC20 INT[5]* Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet Pin Function Pin N2 Vcclnt N3 N21 SysAD[51] N22 P2 SysAD[45] ...
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... Ordering Information RM7000A -123 T Valid Combinations RM7000A-300T RM7000A-350T RM7000A-400T RM7000A-350TI Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002227, Issue 2 RM7000A™ Microprocessor with On-Chip Secondary Cache Data Sheet I Temperature Grade: (blank) = commercial I = Industrial Package Type: ...