RTL8019AS REALTEK, RTL8019AS Datasheet
RTL8019AS
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RTL8019AS Summary of contents
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... Controller with Plug and Play Function REALTEK SEMICONDUCTOR CO., LTD. NO. 11, INDUSTRY E. RD. IX, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU 30077, TAIWAN, R.O.C. TEL:886-35-780211 FAX:886-35-776047 TEL: 886-2-2980098 FAX: 886-2-2980094, 2980097 2005-08-26 RTL8019AS RTL8019AS-LF (RealPNP) DATASHEET HEAD OFFICE OFFICE 3F, NO. 56, WU-KUNG 6 RD., TAIPEI HSIEN, TAIWAN, R.O.C. 1 RTL8019AS Datasheet ...
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... REGISTER DESCRIPTIONS 5.1. Group 1: NE2000 Registers 5.1.1. Register Table 5.1.2. Register Functions 5.1.2.1. NE2000 Compatible Registers 5.1.2.2. RTL8019AS Defined Registers 5.2. Group 2: Plug and Play (PnP) Registers 5.2.1. Card Control Registers 5.2.2. Logical Device Control Registers 5.2.3. Logical Device Configuration Registers 6 ...
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... Supports auto polarity correction for 10BaseT Support 8 IRQ lines Supports 16 I/O base address options ─ and extra I/O address fully decode mode (RTL8019AS only) Supports 16K, 32K, 64K and 16K-page mode access to BROM (up to 256 pages with 16K bytes/page) Supports BROM disable command to release memory after remote boot ...
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... Besides, the BROM disable command is provided to release the BROM memory space for other system usage (e.g. EMM386, etc.) after the BROM program is loaded. The RTL8019AS is built in with 16K-byte SRAM in a single chip designed not only to provide more friendly functions but also to save the effort of SRAM sourcing and inventory. ...
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... PIN CONFIGURATION 3.1. Package Identification Lead-free package is indicated by an ‘L’ in the location marked ‘T’ in the figure above. 2005-08-26 5 RTL8019AS Datasheet ...
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... High active hardware reset signal from the ISA bus. Pulses with high level less than 800ns are ignored. I Host address bus. SA10 is added to implement the fully decode of PnP ports, address 279h and A79h. In RTL8019, SA10 is not decoded. In RTL8019AS, SA10 should be 0 for a valid access to PnP ports. I/O Host data bus. I Host memory read command ...
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... After RTL8019AS latches all jumper status upon power on reset, these pins always* reflect the value of BPAGE register directly in BROM page mode. In normal mode, BA16-21 are not used and BA14-15 act as: BROM Size 16K 32K 64K *Note: RTL8019AS doesn't drive BA14-21 until the SMEMRB goes from high to low ...
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... AUI interface. The input should be driven low for embedded BNC and high for external MAU. When the input is high, RTL8019AS sets the AUI bit (bit5) in CONFIG0 and drives LEDBNC low to disable the BNC. If this pin is not used, it should be connected to GND such that RTL8019AS acts like RTL8019 ...
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... Register Descriptions The registers in RTL8019AS can be roughly divided into two groups by their address and functions -- one for NE2000, the other for Plug and Play (PnP). 5.1. Group 1: NE2000 Registers This group includes 4 pages of registers which are selected by bit PS0 & PS1 in the CR register. ...
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... FB5 FB4 FB14 FB13 FB12 FB22 FB21 FB20 FB30 FB29 FB28 FB38 FB37 FB36 FB46 FB45 FB44 FB54 FB53 FB52 FB62 FB61 FB60 10 RTL8019AS Datasheet Bit 3 Bit 2 Bit 1 Bit 0 RD0 TXP STA STP A11 A10 A9 A8 A11 A10 A9 A8 A11 A10 ...
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... IRQS1 IRQS0 - - - PL0 BSELB BS4 PL0 BSELB - FUDUP LEDS1 LEDS0 - - - CSN6 CSN5 CSN4 HLT6 HLT5 HLT4 INT6 INT5 INT4 - - - 11 RTL8019AS Datasheet Bit 3 Bit 2 Bit 1 RD0 TXP STA STP A11 A10 A9 A8 A11 A10 A9 A8 A11 A10 SEP ATD LB1 LB0 CRC ...
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... Description PS1 PS0 Register Page RD2 RD1 RD0 STA STP Function 1 0 Start Command 0 1 Stop Command Description 12 RTL8019AS Datasheet Remark NE2000 compatible NE2000 compatible NE2000 compatible RTL8019AS Configuration Function Not allowed Remote Read Remote Write Send Packet Abort/Complete remote DMA ...
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... This register indicates the status of a packet transmission. 2005-08-26 Description Description LB1 LB0 Mode Conditions CRC Logic Activities Mode CRC Generator 0 normal enabled 1 normal disabled 0 loopback enabled 1 loopback disabled 13 RTL8019AS Datasheet Remark Normal Operation Internal Lookback External Lookback External Lookback CRC Checker enabled enabled disabled enabled ...
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... These two registers can be read to get the current local DMA address. PSTART: Page Start Register (01H; Type=W in Page0, Type=R in Page 2) The Page Start register sets the start page address of the receive buffer ring. PSTOP: Page Stop Register (02H; Type=W in Page0, Type=R in Page2) 2005-08-26 Description Description Description 14 RTL8019AS Datasheet ...
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... Current Page Register (07H; Type=R/W in Page1) This register points to the page address of the first receive buffer page to be used for a packet reception. MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in Page1) These registers provide filtering bits of multicast addresses hashed by the CRC logic. 2005-08-26 15 RTL8019AS Datasheet ...
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... RTL8019AS Defined Registers Page 0 (PS1=0, PS0=0) Two registers are defined to contain the RTL8019AS chip ID. No. Name 0AH 8019ID0 0BH 8019ID1 Page 3(PS1=1, PS0=1) Page3 Power Up Values before loading jumper states and 9346 contents No. Name Type 00H CR R/W 01H 9346CR R/W ...
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... EECS, EESK,EEDI, & EEDO pins respectively Config register write enable: Before writing to the Page3 CONFIG1-3 registers, the RTL8019AS must be placed in this mode. This will prevent RTL8019AS's configurations from accidental change. 17 RTL8019AS Datasheet Operating Mode ...
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... CONFIG0: RTL8019AS Configuration Register 0 (03H; Type=R except Bit[7:6]=R/W) Bit Symbol 7-6 VERID Version ID: These two bits are defined as below. 5 AUI This bit is set when external MAU is used on AUI interface. Therefore it is set when in 10Base5 mode or the AUI input pin is high. ...
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... This bit's power-up initial value is 1 and may be modified by software if EEM1=EEM0=1 in 9346CR register. 6-4 IRQS2-0 IRQ Select : These 3 bits select one of INT7-0 to reflect the RTL8019AS's interrupt request status. All unselected interrupt lines will be tri-stated. 3-0 IOS3-0 Select I/O base address. 2005-08-26 ...
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... BS4-0 These bits select the BROM size & memory base address. The RTL8019AS supports a special BROM mode: page mode. In page mode, the BROM always occupies 16K-byte host memory space. However the actual BROM size can bytes. The BROM is divided into several 16K-byte pages. The power on boot page is set to page 0 and the program in page 0 is responsible to select the other pages by the BPAGE register and load their programs ...
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... Symbol 7 PNP This bit is negligible in jumper mode. In jumperless mode it, when set, indicates the RTL8019AS is operating in Plug and Play mode. This bit is set when the PNP pin is high or the PNP bit in 9346 is set in jumperless mode. 6 FUDUP When this bit is set, RTL8019AS is set to the full-duplex mode which enables simultaneously transmission and reception on the twisted-pair link to a full-duplex Ethernet switching hub ...
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... HLTCLK: Halt Clock Register (09H; Type=W) This is the only active one of Group1 registers when RTL8019AS is inactivated. Writing to this register is invalid if RTL8019AS is not in power down mode. (i.e. If PWRDN bit in CONFIG3 register is zero.) The data written to this register determines the RTL8019AS's power down mode. ...
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... Furthermore, all card registers are card control registers, while the logical device registers can be divided into logical device control registers and configuration registers. Although an RTL8019AS card contains only one logical device, the following paragraph still depicts the Plug and Play registers by the same PnP categorizing method. ...
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... Wake[CSN] command. The CSN value written to this register will also be recorded to the CSNSAV register located at PnP register index F5H and Group 1 Page3 offset 08H. R 00H (Only one logical device in RTL8019AS). 24 RTL8019AS Datasheet Definition ...
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... BROM base address bits[23:16] 41H BROM base address bits[15:0] 42H Memory Control Note: The BROM size of RTL8019AS is determined by the 9346 contents but not the memory configuration registers. I/O Configuration Registers Index Name 60H I/O base address bits[15:8] 61H I/O base address bits[7:0] ...
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... Direct mapping of the Page3 CONFIG3 register Direct mapping of the Page3 CSNSAV register. W Bit[ Reset CSN command Setting this bit will reset the card's CSN in the CSN register (index 06H The CSNSAV register is not affected. This bit is cleared by hardware automatically. 26 RTL8019AS Datasheet Definition Definition ...
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... PnP jumper used. In RTL8019AS, we change RTL8019's original specification into: The ACTIVEB bit in 9346 is ignored when RTL8019AS is in jumper or RT jumperless mode. The adapter's power-up status is always "ACTIVE" jumperless mode. However, the active status still can be changed via the PnP Activate register. ...
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... BS2 0 jumper jumper jumper 0 9346 9346 9346 Bit 5 Bit 4 Bit 3 Bit 2 - SLEEP PWRDN ACTIVEB 9346 9346 - 0 9346 9346 - 0 28 RTL8019AS Datasheet Bit 1 Bit 0 IOS1 IOS0 jumper jumper 9346 9346 Bit 1 Bit 0 BS1 BS0 jumper jumper 9346 9346 Bit 1 Bit 0 9346 9346 ...
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... The Plug and Play logic is quiescent on power up and must be enabled by software. This is done by a predefined series of writes (32 I/O writes) to the ADDRESS port, which is called the initiation key. The write sequence is decoded by RTL8019AS. If the proper series of I/O writes is detected, then the Plug and Play auto-configuration ports are enabled. The write sequence will be reset and must be issued from the beginning if any data mismatch occurs ...
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... State Isolation Get one bit from serial identifier yes ID bit="1H" Leave SD [7:0] in high-impedance no Wait for next read from serial isolation register Leave SD [7:0] in high impedance no 30 RTL8019AS Datasheet no SD[1:0]="01" yes SD[1:0]="10" yes ID=0 other card ID=1 State Sleep ...
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... The above sequence is repeated for the entire 72-bit serial identifier. 2005-08-26 The serial identifier is a 72-bit unique, non-zero number Byte 0 Byte 3 Byte 2 7:0 7:0 7:0 7:0 Figure 2. Shifting of Serial Identifier 31 RTL8019AS Datasheet Vendor ID Byte 1 Byte 0 7:0 7:0 Shift ...
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... All other results are assumed "0". During the first 64 bits, software generates a checksum using the received data. The checksum is compared with the checksum read back in the last 8 bits of the sequence. 2005-08- Figure 3. Checksum LFSR 32 RTL8019AS Datasheet Shift out ...
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... NOTE: The software must delay 1 msec prior to starting the first pair of isolation reads, and must wait 250 msec between each subsequent pair of isolation reads. This delay gives the ISA card time to access information from possibly very slow storage devices. 2005-08-26 33 RTL8019AS Datasheet ...
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... Active Commands Reset Sleep Reset CSN Wait for Key Wake [CSN] Lose serial isolation OR (WAKE<>CSN) Active Commands Set CSN 34 RTL8019AS Datasheet (WAKE<>0) AND (WAKE=CSN) WAKE<>CSN State Active Commands Reset Reset CSN Wait for Key Config Wake [CSN] Resource Data ...
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... There is a required 2 msec delay from either a RSTDRV or a PnP Reset command to any Plug and Play port access to allow a card to load initial configuration information from a non-volatile device, which is 9346 for RTL8019AS. Cards in the Wait for Key state do not respond to any access to their auto-configuration ports until the initiation key is detected ...
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... P.S. PCs with PnP BIOS, or Windows 95, or Intel Configuration Manager, etc. are called PnP PCs If a card in mode(2.1) is put in a non-PnP PC, the drivers will fail to initialize the card. RTL8019AS supports a PnP auto-detect mode to solve the problem. The card may be set to a default state: PnP mode & power-on active with BROM disabled. If the card non-PnP PC, it will work like a normal jumperless card ...
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... CONFIG1 * IRQS2 CONFIG2 PL1 PL0 CONFIG3 PNP FUDUP P.S. '*' denotes don't care. Example : Plug and Play Resource Data for RTL8019AS (Total 73+5 bytes) TAG Plug and Play Version Number Item byte PnP version Vendor version TAG ANSI Identifier String Item byte ...
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... Checksum 6.4. Boot ROM Whether a EPROM or flash memory is used as the BROM, RTL8019AS's BROM read operation is still the same as RTL8019's. The supported BROM size is the same, too. The write operation of a flash memory is much like the read except that a SMEMWB command is issued instead of SMEMRB ...
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... In this case, the BROM page mode is used. Before either to read or write BROM, the appropriate ROM page must be set in the BPAGE (page3, offset 02h) register first. The RTL8019AS will always reflect the content of BPAGE onto the BA14-21 bus. When RTL8019AS decodes a valid BROM read or write command, it asserts BCSB low ...
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... LEDS1 and LEDS0 bits in the Page3 CONFIG3 register. P. assumed that the LED is on when the signal goes low. (1) LED_TX: Tx LED (2) LED_RX: Rx LED 2005-08-26 Power On LED=low Transmitting Packet? Yes + LED=high for (100 10 LED=low for ( Power On LED=low Receiving Packet? Yes + LED=high for (100 10 LED=low for ( RTL8019AS Datasheet No No ...
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... LED_CRS=LED_TX+LED_RX: Carrier Sense LED (4) LED_COL: Collision LED 2005-08-26 Power On LED=low Packet? Yes + LED=high for (100 10 LED=low for ( Power On LED=high Collision (except Heartbeat)? Yes + LED=low for ( RTL8019AS Datasheet No No ...
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... LED_CRS 6.6. Loopback Diagnostic Operation 6.6.1. Loopback operation The RTL8019AS provides 3 loopback modes. By loopback test, we can verify the integrity of data path, CRC logic, address recognition logic and cable connection status. Mode 1: Loopback through the NIC (LB1=0, LB0=1 in TCR). The NRZ data is not transmitted to the SNI but instead it's loopbacked to the NIC's Rx deserializer ...
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... Note: Loopback mode 3 is sensitive to the network traffic, so the values of FIFO may be not correct. (2) To verify CRC logic Select a loopback mode (e.g. mode 2) to test A. To test CRC generator set RCR=00h to accept physical packet set PAR0-5 to accept packet set TCR=04h (CRC enabled) 2005-08-26 SNI MAU 83910 8392/RTL8005 43 RTL8019AS Datasheet CABLE ...
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... Expected: ISR=06h (packets accepted, Rx CRC error) B. Wrong physical destination address set RCR=00h to accept physical packet set PAR0-5 to reject packet set TCR=04h (CRC enabled) set DCR=40h (8-bit slot) or 43h (16-bit slot) clear ISR tx a packet check ISR after loopback Expected: ISR=02h (packets rejected response) 2005-08-26 44 RTL8019AS Datasheet ...
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... If MAU not connected, get TSR=53h (Carrier sense is lost during transmission and CD heartbeat fails.). C. 10BaseT with link test disabled RTL8019AS disables link test in this case, so cable OK or FAIL doesn't affect TSR; get TSR=03h. D. Auto-detection (10BaseT with link test enabled) RTL8019AS automatically switches from 10BaseT to 10Base 2 if the twisted-pair wire is not connected (10BaseT link test fails). If twisted-pair wire OK, get TSR=03h (Tx OK) & ...
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... Note 2: Apply only to MD7 ~ MD0, MA13 ~ MA0, LED Pins, EECS, MWRB, MRDB, BCSB. Note 3: Apply only to IOCHRDY, IOCS16B 2005-08-26 Min. Typ. Max. 0.8 2.0 0.4 0.6 3.0 3.5 0.4 0.6 3.5 4.0 0.6 50 100 150 - RTL8019AS Datasheet Unit Conditions Iol=16mA, Note 1 V Ioh=8mA, Note 1 V Iol=4mA, Note 2 V Ioh=4mA, Note 2 V Iol=24mA, Note ...
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... IOWB when no wait state insertion is needed. T5 Read data valid to IOCHRDY high when wait state is needed T6 Read data hold after IORB rising edge T7 Write data setup to IOWB rising edge T8 Write data hold from IOWB rising edge 2005-08- Min. Typ RTL8019AS Datasheet Max. Unit ...
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... IOCHRDY low width T3 SMEMRB low to BA14-21 valid T4 SMEMRB low to BCSB valid T5 BA14-21 hold from SMEMRB rising edge T6 BCSB hold from SMEMRB rising edge T7 Read data hold from SMEMRB rising edge 2005-08- Min. - 125 - - - - - 48 RTL8019AS Datasheet Typ. Max. Unit - 30 ns 200 350 ...
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... REALTEK Semiconductor Co., Ltd. REALTEK reserves the right to change products or specifications without notice. This document has been carefully checked and is believed to be accurate. However REALTEK Semiconductor Co., Ltd. assumes no responsibility for inaccuracies. 2005-08-26 Min. Typ. Max 3 RTL8019AS Datasheet Unit ...
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... Millimeter 4.General appearance spec. should be based on final visual inspection spec. TITLE : 100L QFP ( 14x20 mm**2 ) FOOTPRINT 4.8 mm APPROVE CHECK 0.10 － REALTEK SEMI-CONDUCTOR CO., LTD 12 ° 50 RTL8019AS Datasheet PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: DWG NO. REV NO. SCALE Ricardo Chen DATE SHT NO ...
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... Part Number RTL8019AS RTL8019AS-LF Note: See page 5 for package identification information. Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw 2005-08-26 Package 100-Pin QFP RTL8019AS in Lead (Pb)-Free Package 51 RTL8019AS Datasheet Status ...