RTL8201CP REALTEK, RTL8201CP Datasheet
RTL8201CP
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RTL8201CP Summary of contents
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... RTL8201CP SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER (With Auto Crossover) DATASHEET Rev. 1.1 26 September 2003 Track ID: JATR-1076-21 ...
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... Realtek representative for additional information that may help in the development process. REVISION HISTORY Revision Release Date 1.0 2003/06/09 1.1 2003/09/26 Single-Chip/Port 10/100 Fast Ethernet PHYceiver Summary First release. Minor cosmetic changes. Modify LED Pin behavior. ii RTL8201CP Datasheet Track ID: JATR-1076-21 Rev. 1.1 ...
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... E M YPASS ECEIVER RROR ASK (REC) .................................................................................................................... 13 OUNTER R ...................................................................................................................... 13 EGISTER .................................................................................................................................... 13 I ......................................................................................................................... 14 NTERFACE P D ...................................................................................................... 16 ARALLEL ETECTION ......................................................................................................................................... ............................................................................................ 18 UTO EGOTIATION C ............................................................................................................... 19 ONFIGURATION ................................................................................................................................... OWER AVING AND SOLATION .................................................................................................................................... 22 B ..................................................................................................................................... 22 IAS ...................................................................................... 22 OLTAGE ONVERSION IRCUIT ...................................................................................................................................... 22 iii (ANAR) ................................................................... 10 (ANLPAR) ..................................................... 10 EGISTER R (LBREMR) ................................................ 12 EGISTER M ..................................................................... 20 ODES Track ID: JATR-1076-21 Rev. 1.1 RTL8201CP Datasheet ...
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... Table 22. Setting the Medium Type and Interface Mode to MAC ............................................................. 16 Table 23. UTP Mode and MII Interface ..................................................................................................... 16 Table 24. UTP Mode and SNI Interface ..................................................................................................... 17 Table 25. Fiber Mode and MII Interface..................................................................................................... 17 Single-Chip/Port 10/100 Fast Ethernet PHYceiver ..................................................................................................................................... 30 ............................................................................................................................ 30 N ............................................................................................................................ 32 OTES List of Tables iv RTL8201CP Datasheet Track ID: JATR-1076-21 Rev. 1.1 ...
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... Figure 12. SNI Transmission Cycle Timing-2............................................................................................ 27 Figure 13. SNI Reception Cycle Timing-1 ................................................................................................. 28 Figure 14. SNI Reception Cycle Timing-2 ................................................................................................. 28 Figure 15. MDC/MDIO Timing.................................................................................................................. 29 Figure 16. MDC/MDIO MAC to PHY Transmission Without Collision................................................... 29 Figure 17. MDC/MDIO PHY to MAC Reception Without Error .............................................................. 30 Single-Chip/Port 10/100 Fast Ethernet PHYceiver List of Figures v RTL8201CP Datasheet Track ID: JATR-1076-21 Rev. 1.1 ...
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... Ethernet MAC that needs a UTP physical connection or Fiber PECL interface to an external 100Base-FX optical transceiver module. 2. Features The Realtek RTL8201CP is a Fast Ethernet PHYceiver with selectable MII or SNI interface to the MAC chip. It provides the following features: Pin-to-pin compatible with the RTL8201BL ...
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... Voltage Figure 1. Block Diagram 2 Descrambler Scrambler Link pulse 10M Output waveform shaping Receive low pass filter 3 Level Driver Peak Detect Adaptive Equalizer Master PPL 25M Track ID: JATR-1076-21 Rev. 1.1 RTL8201CP Datasheet RXD RXC 25M TXD TXC 25M TXO+ TXO - RXIN+ RXIN- ...
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... Pin Assignments 37. ANE 38. DUPLEX 39. SPEED 40. RPTR 41. LDPS 42. RESETB 43. ISOLATE 44. MII/SNIB 45. DGND 46. X1 47. X2 48. DVDD33 Single-Chip/Port 10/100 Fast Ethernet PHYceiver RTL8201CP Figure 2. Pin Assignments 3 RTL8201CP Datasheet 24. RXER /FXEN 23. CRS 22. RXDV 21. RXD0 20. RXD1 19. RXD2 18. RXD3 17. DGND 16. RXC 15. LED4/ PHYAD4 14. DVDD33 13. LED3/ PHYAD3 Track ID: JATR-1076-21 Rev. 1.1 ...
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... This pin provides a clock synchronous to MDIO, which may be asynchronous to the transmit TXC and receive RXC clocks. The clock rate can 2.5MHz. Management Data Input/Output. This pin provides the bi-directional signal used to transfer management information. 4 RTL8201CP Datasheet I: Input Track ID: JATR-1076-21 Rev. 1.1 ...
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... Transmit Bias Resistor Connection. This pin should be pulled to GND by a 2KΩ (1%) resistor to define driving current for the transmit DAC. The resistance value may be changed, depending on experimental results of the RTL8201CP. Receive Input. Differential receive input pair shared by 100Base-TX, 100Base-FX, and 10Base-T modes. ...
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... LED Interface/PHY Address Configuration These five pins are latched into the RTL8201CP during power up reset to configure the PHY address [0:4] used for the MII management register interface. In normal operation, after initial reset, they are used as driving pins for status indicator LEDs. The driving polarity, active low or active high, is determined by each latched status of the PHY address [4:0] during power-up reset ...
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... Then connect this pin through a ferrite bead to PWFBIN (pin8). The connection method is outlined in 7.11 3.3V Power Supply and Voltage Conversion Circuit, page 22.. Power Feedback Input: see the PWFBOUT description above. Not Connected. 7 RTL8201CP Datasheet Track ID: JATR-1076-21 Rev. 1.1 ...
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... Register Descriptions This section describes the functions and usage of the registers available in the RTL8201CP. In this section the following abbreviations are used: RO: Read Only RW: Read/Write 6.1. Register 0 Basic Mode Control Register Table 9. Register 0 Basic Mode Control Register Address Name Description 0:15 Reset This bit sets the status and control registers of the PHY in a default state ...
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... Jabber condition detected 0: No jabber condition detected 0: Basic register capability only Table 11. Register 2 PHY Identifier Register 1 Description PHY identifier ID for software recognition of the RTL8201CP Table 12. Register 3 PHY Identifier Register 2 Description PHY identifier ID for software recognition of the RTL8201CP 9 RTL8201CP Datasheet Mode Default RO 0 ...
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... Link partner is indicating a remote fault 0: Link partner does not indicate a remote fault 5:12 Reserved 5:11 TXFC 1: TX flow control is supported by Link partner 0: TX flow control not supported by Link partner Single-Chip/Port 10/100 Fast Ethernet PHYceiver 10 Track ID: JATR-1076-21 Rev. 1.1 RTL8201CP Datasheet Mode Default ...
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... This bit is set when a new Link Code Word Page has been received automatically cleared when the auto-negotiation link partner’s ability register (register 5) is read by management. 6:0 LP_NW_ABLE 1: Link partner supports NWay auto-negotiation. Single-Chip/Port 10/100 Fast Ethernet PHYceiver 11 Track ID: JATR-1076-21 Rev. 1.1 RTL8201CP Datasheet Mode Default ...
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... Register (LBREMR) Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR) Address Name Description 17:15 RPTR Set put the RTL8201CP into repeater mode 17:14 BP_4B5B Assertion of this bit allows bypassing of the 4B/5B & 5B/4B encoder. 17:13 BP_SCR Assertion of this bit allows bypassing of the scrambler/descrambler ...
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... No 10Base-T link established 25:0 LINK100 1: 100Base-FX or 100Base-TX link established 0: No 100Base link established Single-Chip/Port 10/100 Fast Ethernet PHYceiver Table 18. Register 18 RX_ER Counter (REC) Table 19. Register 19 SNR Display Register Table 20. Register 25 Test Register 13 RTL8201CP Datasheet Mode Default RW H’[0000] Mode Default RW 0000 ...
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... MII and Management Interface 7.1.1. Data Transition To set the RTL8201CP for MII mode operation, pull MII/SNIB pin high and set the ANE, SPEED, and DUPLEX pins. The MII (Media Independent Interface 18-signal interface (as described in IEEE 802.3u) supplying a standard interface between the PHY and MAC layer. This interface operates at two frequencies – ...
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... RTL8201CP devices, configured with different PHY addresses (00001b to 11111b). During a hardware reset, the logic levels of pins 9, 10, 12, 13, 15 are latched into the RTL8201CP to be set as the PHY address for management communication via the serial interface. Setting the PHY address to 00000b will put the RTL8201CP into power down mode ...
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... RTL8201CP will enable half duplex mode and enter parallel detection mode. The RTL8201CP will default to transmit FLP (Fast Link Pulse) and wait for the link partner to respond. If the RTL8201CP receives FLP, then the auto-negotiation process will go on receives NLP (Normal Link Pulse), then the RTL8201CP will change to 10Mbps and half duplex mode ...
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... ANAR register using the MDC/MDIO SMI interface, then the RTL8201CP will add the ability to its NWay ability. If the Link partner also supports Flow Control, then the RTL8201CP can recognize the Link partner’s NWay ability by examining bit 10 of ANLPAR (register 5). ...
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... Pull high to set the RTL8201CP into repeater mode. This pin is pulled low by default (see 7.9 Repeater Mode Operation, page 22. LDPS Pull high to set the RTL8201CP into LDPS mode. This pin is pulled low by default (see 7.7 Power Down, Link Down, Power Saving, and Isolation Modes, page 20). MII/SNIB Pull high to set RTL8201CP into MII mode operation, which is the default mode for the RTL8201 ...
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... LED and PHY Address Configuration In order to reduce the pin count on the RTL8201CP, the LED pins are duplexed with the PHY address pins. Because the PHYAD strap options share the LED output pins, the external combinations required for strapping and LED usage must be considered in order to avoid contention. Specifically, when the LED outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic level sampled by the corresponding PHYAD input upon power-up/reset ...
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... Description Analog Off Setting bit 11 of register will put the RTL8201CP into analog off state. In analog off state, the RTL8201CP will power down all analog functions such as transmit, receive, PLL, etc. However, the internal 25MHz crystal oscillator will not be powered down. Digital functions in this mode are still ...
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... RTL8201CP and then transmitted. 10Base-T Receive Function In 10Base-T receive mode, the Manchester decoder in the RTL8201CP converts the Manchester encoded data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then, the serial NRZ data stream is converted to a parallel 4-bit nibble signal (RXD[0:3]) ...
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... Repeater Mode Operation Setting bit 15 of register pulling the RPTR pin high, sets the RTL8201CP into repeater mode. In repeater mode, the RTL8201CP will assert CRS high only when receiving a packet. In NIC mode, the RTL8201CP will assert CRS high both when transmitting and receiving packets. If using the RTL8201CP in a NIC or switch application, set to the default mode ...
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... Table 28. Absolute Maximum Ratings Minimum Typical 3.0V 3.3V -55 C Table 29. Operating Conditions Minimum 3. Table 30. Power Dissipation Table 31. Input Voltage: Vcc IOH=-8mA IOL=8mA Vout=Vcc or GND Vin=Vcc or GND 23 RTL8201CP Datasheet Maximum 3.6V 125 C Typical Maximum 3.3V 3. Total Current Consumption TBD TBD TBD TBD TBD TBD ...
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... Figure 7. MII Transmission Cycle Timing-1 24 RTL8201CP Datasheet Typical Maximum Unit 20 26 200 260 20 26 200 260 40 400 400 160 2000 70 140 400 100 170 t ...
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... Figure 8. MII Transmission Cycle Timing-2 Table 33. MII Reception Cycle Timing Minimum 100Mbps 14 10Mbps 140 100Mbps 14 10Mbps 140 100Mbps 10Mbps 100Mbps 10 10Mbps 6 100Mbps 10 10Mbps 6 100Mbps 10Mbps 100Mbps 10Mbps 100Mbps 10Mbps 100Mbps 10Mbps 25 RTL8201CP Datasheet Typical Maximum Unit 200 260 200 260 400 130 ...
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... Figure 9 shows an example of a packet transfer from PHY to MAC on the MII interface. RXCLK RXD[0:3] RXDV RXER RXCLK RXDV RXD[0:3] CRS TPRX+- Single-Chip/Port 10/100 Fast Ethernet PHYceiver Figure 9. MII Reception Cycle Timing Figure 10. MII Reception Cycle Timing-2 26 RTL8201CP Datasheet IH(min L(max H(min L(max Track ID: JATR-1076-21 Rev. 1.1 ...
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... TXCLK TXD0 TXEN TXCLK TXEN TXD0 TPTX+- Single-Chip/Port 10/100 Fast Ethernet PHYceiver Table 34. SNI Transmission Cycle Timing Figure 11. SNI Transmission Cycle Timing Figure 12. SNI Transmission Cycle Timing-2 27 Minimum Maximum Unit 120 IH(min) V IL(max H(min L(max Track ID: JATR-1076-21 Rev. 1.1 RTL8201CP Datasheet ...
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... RXCLK RXD0 RXCLK RXD0 CRS TPRX+- Single-Chip/Port 10/100 Fast Ethernet PHYceiver Table 35. SNI Reception Cycle Timing Minimum Figure 13. SNI Reception Cycle Timing Figure 14. SNI Reception Cycle Timing-2 28 RTL8201CP Datasheet Typical Maximum 120 50 160 600 1800 IH(min) V IL(max H(min) V IL(max Track ID: JATR-1076-21 Rev. 1.1 ...
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... Figure 16 shows an example of a packet transfer from MAC to PHY. Figure 16. MDC/MDIO MAC to PHY Transmission Without Collision Single-Chip/Port 10/100 Fast Ethernet PHYceiver Table 36. MDC/MDIO Timing Minimum 160 160 400 Figure 15. MDC/MDIO Timing 29 RTL8201CP Datasheet Maximum Unit 300 H(min L(max IH(min L(max) V IH(min) ...
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... DC resistance (max) Note: To enable the Auto-Crossover Detection Function, a transformer with symmetrical TX/RX schematics plus TX Center Tap shorted to RX Center Tap is necessary, i.e. Pulse Engineer H1245 (refer to the suggested RTL8201CP Schematic available for download at www.realtek.com.tw). Single-Chip/Port 10/100 Fast Ethernet PHYceiver Table 37. Crystal Specifications Range 25 ...
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... Mechanical Dimensions See the following page for drawing related notes. Single-Chip/Port 10/100 Fast Ethernet PHYceiver 31 Track ID: JATR-1076-21 Rev. 1.1 RTL8201CP Datasheet ...
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... TITLE: 48LD LQFP ( 7x7x1.4mm) 7.00 BSC PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm 0.50 BSC LEADFRAME MATERIAL: 0.40 0.60 0.80 APPROVE 1.00 REF 0 3 CHECK 0 12 TYP REALTEK SEMICONDUCTOR CORP. 12 TYP 32 RTL8201CP Datasheet DOC. NO. VERSION 1 PAGE OF DWG NO. SS048 - P1 DATE Track ID: JATR-1076-21 Rev. 1.1 ...