RTL8139CL REALTEK, RTL8139CL Datasheet
RTL8139CL
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RTL8139CL Summary of contents
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... REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT 1. Features: .................................................................. 2 2. General Description................................................ 3 3. Block Diagram ........................................................ 4 4. Pin Assignments...................................................... 5 5. Pin Descriptions ...................................................... 6 5.1 Power Management/Isolation Interface .............. 6 5.2 PCI Interface....................................................... 6 5.3 FLASH/EEPROM Interface ............................... 8 5.4 Power Pins .......................................................... 9 5.5 LED Interface ..................................................... 9 5.6 Attachment Unit Interface .................................. 9 5 ...
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... Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse) Note: The model number of the QFP package is RTL8139C. The LQFP package model number is RTL8139CL. 2002/01/10 Supports auxiliary power-on internal reset ready for remote wake-up when main power still remains off ...
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... Operating System Directed Power Management (OSPM) to achieve the most efficient power management possible. The RTL8139CL is suitable for applications such as CardBus or mobile devices with a built-in network controller. The CIS data can be stored in either a 93C56 EEPROM or expansion ROM. ...
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Block Diagram MAC PCI Interface PHY 10/100 half/full MII Switch Interface Logic Transceiver TXC 25M TXD RXC 25M RXD 2002/01/10 Boot ROM EEPROM Interface Interface Power Control Logic Early Interrupt Threshold Register Interrupt Control Early Interrupt Logic Control Logic ...
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Pin Assignments 84 RTSET 85 GND 86 RXIN- 87 RXIN+ 88 OEB 89 WEB 90 VDD 91 TXD- 92 TXD+ 93 GND ISOLATEB 96 VDD 97 LED2 98 LED1 99 LED0 100 MD7 101 MD6 102 ...
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Pin Descriptions In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation. ...
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DEVSELB S/T/S FRAMEB S/T/S GNTB I REQB T/S IDSEL I INTAB O/D IRDYB S/T/S TRDYB S/T/S PAR T/S 2002/01/10 19 Device Select bus master, the RTL8139C(L) samples this signal to insure that a PCI target recognizes the destination ...
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PERRB S/T/S SERRB O/D STOPB S/T/S RSTB I 5.3 FLASH/EEPROM Interface Symbol Type MA16-3 O 70-63, 61, 60, 57, MA8 I/O MA6/9356SEL I/O MA2/EESK O MA1/EEDI O MA0/EEDO O, I EECS O MD0-7 I/O 108, 107, 105-100 ROMCSB O OEB ...
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Power Pins Symbol Type VDD P 1, 12, 25, 35, 46, 58, 59, 106, 109, 119 P GND P 7, 18, 30, 40, 55, 56, 62, 111, 112, 113, 124 P 5.5 LED Interface Symbol Type LED0 ...
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Register Descriptions The RTL8139C(L) provides the following set of operational registers mapped into PCI memory space or I/O space. Offset R/W 0000h R/W 0001h R/W 0002h R/W 0003h R/W 0004h R/W 0005h R/W 0006h-0007h - 0008h R/W 0009h R/W ...
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R /W 0054h-0057h 0058h R/W 0059h R/W 005Ah R/W 005Bh - 005Ch-005Dh R/W 005Eh R 005Fh - 0060h-0061h R 0062h-0063h R/W 0064h-0065h R 0066h-0067h R/W 0068h-0069h R 006Ah-006Bh R 006Ch-006Dh R 006Eh-006Fh R 0070h-0071h R/W 0072h-0073h R 0074h-0075h ...
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R/W 00D9h-00EFh - 00F0h-00F3h R/W 00F4h-00F7h R/W 00F8h-00FBh R 00FCh-00FFh W 6.1 Receive Status Register in Rx packet header Bit R 12 ...
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Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8139C(L) when the Transmit Byte Count (bit12-0) in the corresponding Tx descriptor is written not affected ...
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ERSR: Early Rx Status Register (Offset 0036h, R) Bit R/W 7 6.4 Command Register (Offset 0037h, R/W) This register is used for issuing commands to the RTL8139C(L). These commands are ...
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Interrupt Mask Register (Offset 003Ch-003Dh, R/W) This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt. During a hardware reset, all mask bits are cleared. Setting a ...
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Transmit Configuration Register (Offset 0040h-0043h, R/W) This register defines the Transmit Configuration for the RTL8139C(L). It controls such functions as Loopback, Heartbeat, Auto Transmit Padding, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size. Bit R/W ...
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R/W 3 6.8 Receive Configuration Register (Offset 0044h-0047h, R/W) This register is used to set the receive configuration for the RTL8139C(L). Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. ...
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R/W 10-8 R R/W 4 R/W 3 R/W 2002/01/10 memory. This field sets the threshold level according to the following table: 000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 011 ...
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R/W 1 R/W 0 R/W 6.9 9346CR: 93C46 (93C56) Command Register (Offset 0050h, R/W) Bit R/W 7-6 R/W 4 R/W 2 R 2002/01/10 AM Accept Multicast Packets: This bit allows the receiver to ...
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CONFIG 0: Configuration Register 0 (Offset 0051h, R/W) Bit R 4-3 R 2-0 R 2002/01/10 Symbol SCR Scrambler Mode: Always 0. PCS PCS Mode: Always 0. T10 10 Mbps Mode: Always 0. PL1, ...
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CONFIG 1: Configuration Register 1 (Offset 0052h, R/W) Bit R/W Symbol 7-6 R/W LEDS1-0 5 R/W DVRLOAD 4 R/W LWACT 3 R MEMMAP 2 R IOMAP 1 R/W VPD 0 R/W PMEn 2002/01/10 Description Refer to LED PIN definition. ...
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Media Status Register (Offset 0058h, R/W) This register allows configuration of a variety of device and PHY options, and provides PHY status information. Bit R/W 7 R ...
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R 2002/01/10 Magic Magic Packet: This bit is valid when the PWEn bit of CONFIG1 register is set. The RTL8139C(L) will assert the PMEB signal to wakeup the operating ...
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CONFIG 4: Configuration Register4 (Offset 005Ah, R/W) Bit R/W 7 R/W 6 R/W 5 R R/W 2002/01/10 Symbol RxFIFOAutoClr When set to 1, the RTL8139C(L) will clear the Rx FIFO ...
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Multiple Interrupt Select Register (Offset 005Ch-005Dh, R/W) If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to RTL8139C(L), RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be written ...
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Basic Mode Control Register (Offset 0062h-0063h, R/W) Bit Name 15 Reset Spd_Set 12 Auto Negotiation Enable (ANE) 11- Restart Auto Negotiation 8 Duplex Mode 7-0 - 6.19 Basic Mode Status Register (Offset 0064h-0065h, R) ...
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Auto-negotiation Advertisement Register (Offset 0066h-0067h, R/W) Bit Name ACK 13 RF 12- Pause TXFD 10FD 5 10 4-0 Selector 6.21 Auto-Negotiation Link Partner Ability Register (Offset 0068h-0069h, R) ...
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Auto-negotiation Expansion Register (Offset 006Ah-006Bh, R) This register contains additional status for NWay auto-negotiation. Bit Name 15 MLF 3 LP_NP_ABLE 2 NP_ABLE 1 PAGE_RX 0 LP_NW_ABLE 6.23 Disconnect Counter (Offset 006Ch-006Dh, R) Bit Name 15-0 DCNT 6.24 ...
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RX_ER Counter (Offset 0072h-0073h, R) Bit Name 15-0 RXERCNT 6.27 CS Configuration Register (Offset 0074h-0075h, R/W) Bit Name 15 Testfun 14- HEART BEAT 7 JBEN 6 F_LINK_100 5 F_Connect Con_status 2 Con_status_En ...
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... Enable Unicast Wakeup Frame with mask bytes of only DID field, which is its own physical address. The power-on default value of this bit is 0. FIFO Address Pointer: (Realtek internal use only to test FIFO SRAM) 0: (Power-on) default value. Both Rx and Tx FIFO address pointers are updated in ascending way from 0 and upwards. The initial FIFO address pointer is 0 ...
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Function Event Register (Offset 00F0h-00F3h, R/W) Bit R/W 31- R/W 14 R/W 3-0 - This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3). The Function Event (Offset F0h), Function Event Mask ...
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Function Present State Register (Offset 00F8h-00FBh, R) Bit R/W 31- 14 3-0 - This register is valid only when Card_En=1 (bit3, Config3) and FuncRegEn=1 (bit1, Config3). This read-only register reflects the current state ...
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... After the valid duration of the RSTB pin or auto-load command in 9346CR, the RTL8139C(L) performs a series of EEPROM read operations from the 93C46 (93C56) address 00H to 31H suggested to obtain Realtek approval before changing the default settings of the EEPROM. Bytes ...
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... PHY Parameter 2-T for RTL8139C. Operational register of the RTL8139C(L) is 80h. Reserved. Reserved. Do not change this field without Realtek approval. CIS Pointer. Reserved. Do not change this field without Realtek approval. Checksum of the EEPROM content. Reserved. Do not change this field without Realtek approval. Reserved. Do not change this field without Realtek approval. ...
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Summary of EEPROM Registers Offset Name Type 00h-05h IDR0 – IDR5 R/W* 51h CONFIG0 52h CONFIG1 58h MSRBMCR 63H 59h CONFIG3 5Ah CONFIG4 R/W ...
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PCI Configuration Space Registers 8.1 PCI Configuration Space Table No. Name Type Bit7 00h VID R VID7 01h R VID15 02h DID R DID7 03h R DID15 04h Command R W 05h R W 06h Status R FBBC 07h ...
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... VID: Vendor ID. This field will be set to a value corresponding to PCI Vendor ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI Vendor ID. DID: Device ID. This field will be set to a value corresponding to PCI Device ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 8129h ...
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Bit Symbol 15-10 - Reserved 9 FBTBEN Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The RTL8139C(L) will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, This read/write bit controls whether or not a master can do fast ...
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Bit Symbol 15 DPERR Detected Parity Error: When set indicates that the RTL8139C(L) detected a parity error, even if parity error handling is disabled in command register PERRSP bit. 14 SSERR Signaled System Error: When set indicates that the RTL8139C(L) ...
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BIST: Built-in Self Test Reads will return a 0, writes are ignored. IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also specifies the number of bytes required as well ...
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... Expansion ROM space --- The CIS is stored in expansion ROM physically within the 128KB max. SVID: Subsystem Vendor ID. This field will be set to a value corresponding to the PCI Subsystem Vendor ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 11ECh which is Realtek Semiconductor's PCI Subsystem Vendor ID. ...
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ILR: Interrupt Line Register The Interrupt Line Register is an 8-bit register used to communicate with the routing of the interrupt written by the POST software to set interrupt line for the RTL8139C(L). IPR: Interrupt Pin Register The ...
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R 2Bh R 2Ch SVID R 2Dh R 2Eh SMID R 2Fh R 30h BMAR R W 31h R W 32h R/W 33h R/W 34h Cap-Ptr R 35h | - 3Bh 3Ch ILR R/W 3Dh IPR R 3Eh MNGNT ...
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PCI PMC = C2 F7. If Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above 4 bits are all 0’s. I.e. if 9346 PMC = C2 F7, the PCI ...
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The last byte of the masked bytes of the received Wakeup Frame packet within offset (in 8-bit CRC mode) should match the last byte of the masked bytes of the sample Wakeup Frame ...
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Functional Description 9.1 Transmit Operation The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the ...
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Rx Decapsulation The RTL8139C(L) continuously monitors the network when reception is enabled. When activity is recognized it starts to process the incoming data. After detecting receive activity on the line, the RTL8139C(L) starts to process the preamble bytes based ...
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LED_RX In 10/100 Mbps mode, the LED function is like the RTL8129. 9.10.3 LED_TX 2002/01/10 Power On LED = Low No Receiving Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( ...
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LED_TX+LED_RX 2002/01/10 Power On LED = Low Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( RTL8139C(L) Rev.1.4 ...
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Application Diagram RJ45 Magetics 2002/01/10 EEPROM LED CLK RTL8139C(L) Auxiliary Power PCI INTERFACE 50 RTL8139C(L) DATA BOOT ROM Address Rev.1.4 ...
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Electrical Characteristics 11.1 Temperature Limit Ratings Parameter Storage temperature Operating temperature 11.2 DC Characteristics 11.2.1 Supply Voltage Vcc = 3.0V min. to 3.6V max. Symbol Parameter V OH Minimum High Level Output Voltage V OL Maximum Low Level Output ...
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AC Characteristics 11.3.1 FLASH/BOOT ROM Timing FLASH/BOOT ROM - Read MA17-0 ROMCSB OEB WEB MD7-0 Symbol Description TRC Read Cycle TCE Chip Enable Access Time TACC Address Access Time TOES Output Enable Access Time TCOLZ Chip Enable to Output ...
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FLASH MEMORY - Write SETUPMPROGRAM COMMAND VCC POWER-UP & STANDBY MA17-0 tWC ROMCSB tCH OEB tGHWL tWP WEB tDS DATAOUT MD7-0 =40H Symbol TWC Write Cycle Time TAS Address Set-up Time TAH Address Hold Time TDS Data Set-up Time TDH ...
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PCI Bus Operation Timing: 2002/01/10 Target Read Target Write 54 RTL8139C(L) Rev.1.4 ...
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Configuration Read Configuration Write 55 RTL8139C(L) Rev.1.4 ...
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BUS Arbitration Memory Read 56 RTL8139C(L) Rev.1.4 ...
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Memory Write Target Initiated Termination - Retry 57 RTL8139C(L) Rev.1.4 ...
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Target Initiated Termination - Disconnect Target Initiated Termination - Abort 58 RTL8139C(L) Rev.1.4 ...
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Master Initiated Termination - Abort Parity Operation - one example 59 RTL8139C(L) Rev.1.4 ...
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... TITLE: 128 QFP (14x20 mm ) PACKAGE OUTLINE 0.5 0.75 APPROVE 0.88 1.08 1.60 1.85 CHECK - - 0.10 - REALTEK SEMI-CONDUCTOR CO., LTD 12° 60 RTL8139C(L) -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL: DOC. NO. 530-ASS-P004 VERSION PAGE DWG NO. Q128 - 1 DATE Nov. 4 1999 1 OF Rev.1.4 ...
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... TITLE: 128LD LQFP ( 14x20x1.4 mm*2 ) PACKAGE 14.25 20.25 0.50 BSC APPROVE 16.30 23.30 0.75 CHECK 0.60 1.00 REF 0° 3.5° 9° 61 -CU L/F, FOOTPRINT 2.0 mm LEADFRAME MATERIAL: DOC. NO. VERSION PAGE DWG NO. DATE REALTEK SEMICONDUCTOR CORP. RTL8139C(L) 530-ASS-P004 1 OF LQ128 - 1 Nov. 4.1999 Rev.1.4 ...
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... Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2002/01/10 62 RTL8139C(L) Rev.1.4 ...