SC28L92A1B,557 NXP Semiconductors, SC28L92A1B,557 Datasheet - Page 25

• Manufacturer Part Number: SC28L92A1B,557
• Description: IC UART DUAL W/FIFO 44-PQFP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr
• Type: Dual UARTr

Specifications of SC28L92A1B,557

• Number Of Channels: 2, DUART
• Package / Case: 44-MQFP, 44-PQFP
• Features: False-start Bit Detection
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 0.2304 MBd
• Supply Voltage (max): 3.63 V or 5.5 V
• Supply Voltage (min): 2.97 V or 4.5 V
• Supply Current: 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1211; 935263294557; SC28L92A1B

NXP Semiconductors
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
SC28L92_7
Product data sheet
change input
state of IP7
input port
delta IP3
BRG set
received
set OP7
change
select
break
port
7
7
7
7
7
7
7
7
7
7
CR - Command Register
SR - channel Status Register
IMR - Interrupt Mask Register (enables interrupts)
ISR - Interrupt Status Register
CTPU - Counter/Timer Preset Register, Upper
CTPL - Counter/Timer Preset Register, Lower
ACR - Auxiliary Control Register and change of state control
IPCR - Input Port Change Register
IPR - Input Port Register
SOPR - Set Output Port bits Register (SOPR)
change break
change break
framing error
state of IP6
counter/timer mode and clock source
delta IP2
channel command code
set OP6
select (see
6
B
B
6
6
6
6
6
6
6
6
6
Table 54 on page
state of IP5
parity error
RxRDYB
RxRDYB
delta IP1
FFULLB
set OP5
5
5
5
5
5
5
5
5
5
5
8 MSB of the BRG timer divisor
8 LSB of the BRG timer divisor
overrun error
state of IP4
Rev. 07 — 19 December 2007
TxRDTYB
TxRDTYB
delta IP0
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
44)
set OP4
4
4
4
4
4
4
4
4
4
4
COS interrupt
enable IP3
counter ready change break
counter ready change break
state of IP3
state of IP3
disable Tx
set OP3
TxEMT
3
3
3
3
3
3
3
3
3
3
COS interrupt
enable IP2
state of IP2
state of IP2
enable Tx
set OP2
TxRDY
2
A
A
2
2
2
2
2
2
2
2
2
COS interrupt
enable IP1
state of IP1
state of IP1
disable Rx
RxRDYA
RxRDYA
RxFULL
FFULLA
set OP1
1
1
1
1
1
1
1
1
1
1
SC28L92
© NXP B.V. 2007. All rights reserved.
COS interrupt
enable IP0
state of IP0
state of IP0
enable Rx
TxRDYA
TxRDYA
set OP0
RxRDY
0
0
0
0
0
0
0
0
0
0
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