SC16C554BIBM,151 NXP Semiconductors, SC16C554BIBM,151 Datasheet - Page 18

• Manufacturer Part Number: SC16C554BIBM,151
• Description: IC UART QUAD W/FIFO 64-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C554BIBM,151

• Number Of Channels: 4, QUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3267; 935279067151; SC16C554BIBM-S

NXP Semiconductors
SC16C554B_554DB
Product data sheet
Fig 9.
D7 to D0
Autoflow control (auto-RTS and auto-CTS) example
6.4.1 Auto-RTS (see
6.4.2 Auto-CTS (see
6.4 Autoflow control (see
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input
must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes
active when the receiver needs more data and notifies the sending serial device. When
RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has
space for the data; thus, overrun errors are eliminated using UART 1 and UART 2 from a
SC16C554B/554DB with the autoflow control enabled. If not, overrun errors occur when
the transmit data rate exceeds the receiver FIFO read latency.
Auto-RTS data flow control originates in the receiver timing and control block (see block
diagrams in
level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see
RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an
additional byte after the trigger level is reached (assuming the sending UART has another
byte to send) because it may not recognize the de-assertion of RTS until after it has
begun sending the additional byte. RTS is automatically reasserted once the RX FIFO is
emptied by reading the receiver buffer register. When the trigger level is 14 (see
Figure
the RX line. RTS is reasserted when the RX FIFO has at least one available byte space.
Remark: Auto-RTS is not supported in channel D of the HVQFN48 package, therefore
MCR[5] of channel D should not be written.
The transmitter circuitry checks CTS before sending the next data byte. When CTS is
active, it sends the next byte. To stop the transmitter from sending the following byte, CTS
must be released before the middle of the last stop bit that is currently being sent (see
Figure
control is enabled, CTS level changes do not trigger host interrupts because the device
automatically controls its own transmitter. Without auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error may result.
FIFO
FIFO
TX
RX
UART 1
12), RTS is de-asserted after the first data bit of the 16th character is present on
10). The auto-CTS function reduces interrupts to the host system. When flow
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
Figure 1
FLOW
FLOW
All information provided in this document is subject to legal disclaimers.
Figure
Figure
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
and
RTS
CTS
Rev. 4 — 8 June 2010
RX
TX
Figure
9)
9)
Figure
2) and is linked to the programmed receiver FIFO trigger
9)
TX
CTS
RX
RTS
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
SC16C554B/554DB
FLOW
FLOW
UART 2
FIFO
FIFO
RX
TX
002aaa228
© NXP B.V. 2010. All rights reserved.
Figure
D7 to D0
18 of 58
11),