PSB 2134 H V2.2 Infineon Technologies, PSB 2134 H V2.2 Datasheet - Page 8

• Manufacturer Part Number: PSB 2134 H V2.2
• Description: IC CODEC FILTER 4CHAN MQFP-64
• Manufacturer: Infineon Technologies
• Series: SICOFI®r

Specifications of PSB 2134 H V2.2

• Function: CODEC Filter
• Interface: IOM-2 PCM, SPI
• Number Of Circuits: 4
• Voltage - Supply: 5V
• Current - Supply: 26mA
• Power (watts): 130mW
• Mounting Type: Surface Mount
• Package / Case: 64-QFP
• Includes: Level Metering Function, Tone Generation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Other names: PSB2134HV2.2X; SP000007389; SP000007390

Semiconductor Group
1.3
Pin No. Symbol
Common Pins for all Channels
24
21
52
56
57
31
32
26,30
27,29
23
22
17
18
Pin Definition and Functions
V
GNDD
V
V
V
FSC
BCL
DU
DD
RESET
DCL
CS
DCLK
DDD
DDA12
REF
DDREF
Input (I)
Output (O)
I
I
I
I/O
I
I
I
I/O
I/O
I
I
I
I
Function
+ 5 V supply for the digital circuitry
Ground Digital, not internally connected to
GNDA1,2,(3,4)
All digital signals are referred to this pin
+ 5 V Analog supply voltage for channel 1 and 2
Reference voltage, has to be connected to a 220 nF
cap. to ground, can also be used as virtual ground
for analog inputs and outputs (high-ohmic buffer
needed !!!)
+ 5 V Analog supply voltage (100 nF cap. required)
Frame synchronization clock, 8 kHz, identifies the
beginning of the frame, individual time slots are
referenced to this pin, FSC must be synchronous to
DCL and BCL
IOM-2 bit clock 768 kHz, determines the rate at
which PCM data is shifted into or out of the
PCM-ports
IOM-2 Data Upstream interface. Transmits or
receives PCM data in 8 bit bursts. Both pins must be
connected together.
IOM-2 Data Downstream interface. Transmits or
receives PCM data in 8 bit bursts. Both pins must be
connected together.
Reset input - forces the device to default mode,
active low
Master clock input 1536 kHz, synchronous to FSC,
must be available if the SICOFI2/4-TE is operating
write data, active low
to device, the maximum clock rate is 8192 kHz
-Controller interface: chip select enable to read or
-Controller interface: data clock, shifts data from or
8
1)
PSB 2132
PSB 2134
Overview
09.97
1)