DS21352L+ Maxim Integrated Products, DS21352L+ Datasheet - Page 82

• Manufacturer Part Number: DS21352L+
• Description: IC TXRX T1 1-CHIP 3.3V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21352L+

• Function: Single-Chip Transceiver
• Interface: HDLC, T1
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

15.4.3 TRANSMIT SECTION
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full eight bits has been shifted out, the framer will signal the host
microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a one.
The INT will also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new
value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. The framer
also contains a zero stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016,
communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing
flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically look
for 5 ones in a row. If it finds such a pattern, it will automatically insert a zero after the five ones. The
CCR2.0 bit should always be set to a one when the framer is inserting the FDL. More on how to use the
DS21352/552 in FDL applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER (Address=7E Hex)
[also used to insert Fs framing pattern in D4 framing mode; see Section 15.5]
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis
into the outgoing T1 data stream. The LSB is transmitted first.
15.5 D4/SLC–96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the
device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to
1Ch and the following bits must be programmed as shown: TCR1.2=0 (source Fs data from the TFDL
register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries)
Since the SLC–96 message fields share the Fs–bit position, the user can access the these message fields
via the TFDL and RFDL registers. Please see the separate Application Note for a detailed description of
how to implement a SLC–96 function.
SYMBOL
TFDL7
(MSB)
TFDL7
TFDL0
TFDL6
POSITION
TFDL.7
TFDL.0
TFDL5
NAME AND DESCRIPTION
MSB of the FDL code to be transmitted
LSB of the FDL code to be transmitted
TFDL4
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TFDL3
TFDL2
TFDL1
TFDL0
(LSB)