M25P40-VMP6TGB Micron Technology Inc, M25P40-VMP6TGB Datasheet - Page 13

• Manufacturer Part Number: M25P40-VMP6TGB
• Manufacturer: Micron Technology Inc

Specifications of M25P40-VMP6TGB

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: MLP EP
• Program/erase Volt (typ): 2.3 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

4.5
4.6
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P40 features the following data protection mechanisms:
In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program, and Erase instructions, as all
instructions are ignored except the Release from Deep Power-down instruction.
Section 6.4: Read Status Register
Power On Reset and an internal timer (t
inadvertent changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
after the following events:
–
–
–
–
–
–
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits allow part of
the memory to be configured as read-only.
Hardware Protected Mode (HPM): The Write Protect (W) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be
protected.
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
(RDSR).
PUW
) can provide protection against
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