AK4128AEQP AKM Semiconductor Inc, AK4128AEQP Datasheet - Page 8

• Manufacturer Part Number: AK4128AEQP
• Description: IC SAMPLE RATE CONVERTER 64LQFP
• Manufacturer: AKM Semiconductor Inc
• Series: -r
• Type: Sample Rate Converterr

Specifications of AK4128AEQP

• Applications: Automotive Systems, Home Theater, TV
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 974-1043

Note: All input pins should not be left floating. DVDD1-4 must be connected to the same power supply.
Note 1. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be changed when the PDN
Note 2. In parallel control mode (SPB pin = “L”), IDIF2-0 pins control all SRC1~4 audio interface input formats.
Note 3. In parallel control mode (SPB pin = “L”), the SMUTE pin controls all SRC1~4 soft mute.
Note 4. In parallel control mode (SPB pin= “L”), DEM1-0 pins control all SRC1~4 de-emphasis settings.
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The unused I/O pins should be processed appropriately as below.
MS1242-E-01
No.
60
61
62
63
64
Handling of Unused Pins
pin= “L”.
Pin Name
AVDD
VD18
VSS1
TST3
ILRCK2
In serial control mode (SPB pin = “H”), the setting of IDIF2-0 pins is ignored. The IDIF[12:10] bits setting is
reflected to SRC1, the IDIF[22:20] bits setting is reflected to SRC2, the IDIF[32:30] bits setting is reflected to
SRC3, and the IDIF[42:40] bits setting is reflected to SRC4.
In serial control mode (SPB pin = “H”), the SUMUTE pin setting is ignored. The SMUTE1 bit setting is
reflected to SRC1, the SMUTE2 bit setting is reflected to SRC2, the SMUTE3 bit setting is reflected to SRC3,
and the SMUTE4 bit setting is reflected to SRC4.
In serial control mode (SPB pin= “H”), setting of DEM1-0 pins is ignored. DEM[11:10] bits setting is reflected
to SRC1, DEM[21:20] bits setting is reflected to SRC2, DEM[31:30] bits setting is reflected to SRC3, and
DEM[41:40] bits setting is reflected to SRC4.
Classification
Digital
Pin Name
IBICK2, IMCLK, SDTI3-4, ILRCK3,
IBICK3, ILRCK4, IBICK4, SMUTE,
DITHER, OMCLK/XTI, ILRCK2,
SDA, SCL, CAD0, TST0-3
UNLOCK, SDTO1-4, MCKO, XTO
I/O
O
-
-
I
I
Analog Power Supply Pin, 3.0 ∼ 3.6V
Digital Power Output Pin, Typ 1.8V
Analog Ground Pin
Test Pin.
Input Channel Clock #2 Pin
When the PDN pin= “L”, the DV18 pin outputs “L”. Current must not be taken
from this pin. A 1μF (±30%; including the temperature characteristics) capacitor
should be connected between this pin and DVSS. When this capacitor is polarized,
the positive polarity pin should be connected to the VD18 pin.
This pin should be connected to VSS2-5.
When INAS pin = “L”, this pin should be connected to VSS2-5.
- 8 -
These pins must be connected to VSS2-5.
These pins must be open.
Setting
Function
[AK4128A]
2011/06