AK4128AEQP AKM Semiconductor Inc, AK4128AEQP Datasheet
AK4128AEQP
Specifications of AK4128AEQP
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AK4128AEQP Summary of contents
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The AK4128A is an 8ch digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. The AK4128A has an internal Oscillator and does not need any external ...
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IBICK1 ILRCK1 SDTI1 IBICK2 ILRCK2 SDTI2 IBICK3 ILRCK3 SDTI3 IBICK4 ILRCK4 SDTI4 IMCLK PDN PM1 PM2 CAD0 SPB Figure 1. AK4128A Block Diagram (Synchronous mode INAS pin = “L”) IBICK1 ILRCK1 SDTI1 IBICK2 ILRCK2 SDTI2 IBICK3 ILRCK3 SDTI3 IBICK4 ILRCK4 ...
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Compatibility with AK4126 (1) Specifications Parameter Stereo Inputs Not Available Asynchronous Mode Synchronous Mode Only Internal Clock Internal PLL The PLL2-0 pins must be set according to the PLL reference clock. #61 pin: A pin for external devices of ...
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Pins Pin# AK4126 TEST0 7 TST0 14 TST1 15 TST2 TST3 18 TST4 32 TST5 TST6 47 TEST4 TST8 54 PLL2 55 PLL1 56 PLL0 ...
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Ordering Guide AK4128AEQ AK4128AVQ AKD4128A ■ Pin Layout MCKO 49 TST0 5 0 CAD0 VDD4 5 2 VSS5 5 3 TST1 5 4 SMSEM TST2 5 6 SCL 5 7 SDA 5 8 ...
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No. Pin Name I/O 1 IBICK2 I 2 IMCLK I 3 ILRCK1 I 4 IBICK1 I 5 DVDD1 - 6 VSS2 - 7 SDTI4 I 8 SDTI1 I 9 SDTI2 I 10 SDTI3 I 11 IDIF0 I 12 IDIF1 I ...
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No. Pin Name I/O 34 CM2 I 35 CM1 I 36 CM0 I 37 ODIF1 I 38 ODIF0 I 39 SDTO3 O 40 SDTO2 O 41 SDTO1 O 42 SDTO4 O 43 VSS4 - 44 DVDD3 - 45 OBICK I/ ...
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No. Pin Name I/O 60 AVDD - 61 VD18 O 62 VSS1 - 63 TST3 I 64 ILRCK2 I Note: All input pins should not be left floating. DVDD1-4 must be connected to the same power supply. Note 1. SPB, ...
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Note 5) Parameter Analog Power Supplies: Digital Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Power applied) (Note 7) Storage Temperature Note 5. All voltages with respect to ground. VSS1-5 must be connected to the same ...
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AVDD=DVDD1-4=3.3V; VSS1-5=0V; Signal Frequency = 1kHz; data = 24bit; Measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter SRC Characteristics: Resolution Input Sample Rate Output Sample Rate THD+N (Input = 1kHz, 0dBFS, FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz ...
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AVDD=DVDD1-4=3.0 ∼ 3.6V) Parameter Digital Filter Passband −0.01dB 0.985 ≤ FSO/FSI ≤ 6.000 0.905 ≤ FSO/FSI < 0.985 0.714 ≤ FSO/FSI < 0.905 0.656 ≤ FSO/FSI < 0.714 0.536 ≤ FSO/FSI < 0.656 0.492 ≤ FSO/FSI < 0.536 ...
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AVDD=DVDD1-4=3.0 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Except the SDA pin (Iout=−400μA) Low-Level Output Voltage Except the SDA pin (Iout=400μA) SDA pin (Iout=3mA) Input Leakage Current (Ta= 25°C; AVDD=DVDD1-4=3.0 ∼ 3.6V; C ...
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Input PORT LRCK for Stereo Mode (ILRCK1-4) Frequency Duty Cycle Slave Mode Output PORT LRCK for Stereo Mode (OLRCK) Frequency Slave mode Master mode OMCLK Input 128FSO mode Master mode OMCLK Input 256FSO mode Master mode OMCLK Input 384FSO mode ...
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Output PORT (TDM256 slave mode) OBICK Period OBICK Pulse Width Low Pulse Width High OLRCK Edge to OBICK “↑” OBICK “↑” to OLRCK Edge OBICK “↓” to SDTO1 Output PORT (Stereo Master mode) OBICK Frequency OBICK Duty OBICK “↓” to ...
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Parameter 2 Control Interface Timing (I C Bus): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time ...
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Timing Diagram IMCLK(I) tECLKH OMCLK(I) tCLKH MCKO(O) tMCKH Figure 5. IMCLK, OMCLK, MCKO Clock Timing •Stereo Mode and Slave Mode LRCK1-4(I) IBICK1-4(I) •TDM256 Mode and Slave Mode LRCK1(I) IBICK1(I) MS1242-E-01 1/fECLK tECLKL dECLK = tECLKH (or tECLKL) x fECLK ...
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Stereo Mode and Slave Mode OLRCK(I) OBICK(I) • TDM256 Mode and Slave Mode OLRCK(I) OBICK(I) Figure 7. OLRCK, OBICK, Clock Timing (Slave Mode) • Stereo Mode and Master Mode OLRCK(O) OBICK(O) • TDM256 Mode and Master Mode OLRCK(O) 24bit ...
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ILRCK tBLR IBICK SDTI Figure 9. Input PORT Audio Interface Timing (Stereo Slave mode and TDM256 Slave Mode) O LRCK tBLR O BICK tLRS SDTO Figure 10. Output ...
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OLRCK tMBLR OBICK SDTO1-4 Figure 11. Output PORT Audio Interface Timing (TDM256 Master mode & Stereo Master mode) PDN SDA tLOW tBUF SCL tHD:STA Stop Start MS1242-E-01 tPD Figure 12. Power Down Timing tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start ...
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Synchronous and Asynchronous Modes Setting There are two modes of operation: asynchronous and synchronous modes. The AK4128A is set to Synchronous mode when the INAS pin is “L” and it is set to Asynchronous mode when the INAS pin ...
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IDIF2 IDIF1 Mode Pin Pin (Note 23) (Note 23 Table 2. Input PORT Audio Interface Format (Parallel Control Mode, ...
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ILRCK IBICK(64fs) SDTI( 23:MSB, 0:LSB ILRCK IBICK(64fs) SDTI(i) Don't Care 23:MSB, 0:LSB Note: SDTI is identified as SDTI1, SDTI2, SDTI3 and SDTI4, ILRCK is identified as ILRCK1, ILRCK2, ILRCK3 and ILRCK4, IBICK ...
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System Clock for Output PORT The output ports work in master mode and slave mode. The CM2-0 pins select the master/slave mode. CM2 CM1 CM0 Mode Master / Slave pin pin pin ...
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Master Mode The OLRCK pin and OBICK pin are output pins in master mode. Master clock is supplied from the OMCLK/XTI pin. The clock for the OMCLK/XTI pin can be generated by the following methods: Connect a crystal oscillator ...
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SRC Bypass Mode SRC bypass mode can be set in Synchronous inputs mode (INAS pin = “L”). Asynchronous inputs mode (INAS pin = “H”) does not supports SRC bypass mode, so that the data is not transferred correctly on ...
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When the AK4128A is in master mode, SDTI1-4 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode (Table 2). The SDTI1-4 output data are output by the ILRCK1 and IBICK1 clocks in a format shown in ...
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Audio Interface Format for Output PORT The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2’s complement format. The SDTO1-4 is clocked out on the falling edge ...
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OLRCK OBICK(64fs) SDTO(O) 15:MSB, 0:LSB 17 16 SDTO(O) 17:MSB, 0:LSB SDTO( 19:MSB, 0:LSB SDTO( 23:MSB, 0:LSB OLRCK 0 1 ...
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OLRCK(O) OBICK(O) (256FSO) SDTO 1 ( 32OBICK Figure 28. TDM 256 mode 24bit MSB justified Timing at Master Mode. (SDTO2-4: “L” outputs) min. 1/ 256FSO OLRCK(I) OBICK(I) (256FSO) SDTO 1 ( ...
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Mode The AK4128A has 6-channel and 4-channel modes to reduce power supply current when not using all eight channels. When the PM2 and PM1 pins are set to “L/L”, six channels (SDTI1 are powered-up and the other two ...
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Atte n u atio n -∞ Note: SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4. (1) The soft mute cycle ...
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Dither The AK4128A includes a dither circuit. The dither circuit adds a dither signal after the lowest bit of all the output data set by the OBIT1-0 pins when the DITHER pin = “H”, regardless of SRC and SRC ...
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Regulator The AK4128A has an internal regulator which suppresses the voltage to 1.8V from DVDD1-4 voltage. The generated 1.8V power is used as power supply for internal circuit. When over-current is flowed to the regulator output, over-current detection circuit ...
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Case 2: System Reset without clock inputs External clocks (Input port) SDTI External clocks (Output port) PDN (Internal state) Power-down SDTO4 SDTO3 SDTO2 SDTO1 UNLOCK Note 27. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be ...
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Internal Reset Function for Clock Change Clock change timing is shown in Figure 36 When changing the clock, the AK4128A should be reset by the PDN pin in parallel control mode and it should be reset by the PDN ...
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When the frequency of ILRCKx (x= input port is changed without a reset by the PDN pin or RSTN bit. When the difference of internal oscillator (min. 59.4 MHz, typ. 73.5 MHz) clock number in ...
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Internal Status Pin The UNLOCK pin indicates internal status of the device. This pin outputs “H” when the PDN pin = “L”. SRC data is output from SDTO1-4 pins, which corresponds to the each sampling frequency ratio detected SRC, ...
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Serial Control Interface The AK4128A supports fast-mode I connected to (DVDD1-4 + 0.3)V or less voltage. 1. Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4128A ...
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ACKNOWLEDGE ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitter will release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that ...
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WRITE Operations Set R/W bit = “0” for the WRITE operation of the AK4128A. After receipt of a start condition and the first byte, the AK4128A generates an acknowledge, and awaits the second byte (register address). The second byte ...
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READ Operations Set R/W bit = “1” for the READ operation of the AK4128A. After transmission of the data, the master can read next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt ...
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Register Map Addr Register Name 00H Reset & Mute 01H De-emphasis 02H Input Audio Data Format 1 03H Input Audio Data Format 2 Note 39. All register values are initialized by the PDN pin = “L”. Note 40. Writing ...
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SMUTE4: SRC4 Soft Mute Control 0: Soft Mute Release (default) 1: Soft Mute In serial control mode (SPB pin= “H”), the SMUTE pin setting is ignored. SRC4 reflects the SMUTE4 bit setting. Addr Register Name 01H De-emphasis R/W Default DEM11/10: ...
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Figure 48 and Figure 49 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. • Parallel Control Mode (SPB pin = “L”). •Synchronous Mode (INAS pin ...
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Serial Control Mode (SPB pin = “H”). •Asynchronous Inputs Mode (INAS pin = “H”). • OMCLK/XTI Input= 256FSO, X’tal • Input PORT: Slave mode, IBICK1~4 lock mode (64FSI) Input Audio Interface Format can be set by registers. • Output ...
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Grounding and Power Supply Decoupling The AK4128A requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD1-4 are supplied separately, the power up sequence is not critical. VSS1-5 must be connected to the same ground ...
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Digital Filter Response Example Table 15 shows the examples of digital filter response performed by the AK4128A. Ratio FSO/FSI [kHz] 4.000 192/48.0 1.000 48.0/48.0 0.919 44.1/48.0 0.725 32.0/44.1 0.667 32.0/48.0 0.544 48.0/88.2 0.500 48.0/96.0 0.500 44.1/88.2 0.459 44.1/96.0 0.363 ...
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LQFP(Unit: mm 0.5 0.10 ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS1242-E-01 PACKAGE 12.0 Max 1.85 10.0 1. 0.2±0.1 0.10 M 0°~10° 0.50±0.25 ...
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MS1242-E-01 MARKING (AK4128AEQ) AKM AK4128AEQ XXXXXXX 1 XXXXXXX: Date code identifier MARKING (AK4128AVQ) AKM AK4128AVQ XXXXXXX 1 XXXXXXX: Date code identifier - 49 - [AK4128A] 2011/06 ...
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Date (YY/MM/DD) Revision 10/09/13 00 11/06/02 01 These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) ...