AD8111AST Analog Devices Inc, AD8111AST Datasheet - Page 16

• Manufacturer Part Number: AD8111AST
• Description: IC VIDEO CROSSPOINT SWIT 80LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD8111AST

• Rohs Status: RoHS non-compliant
• Function: Video Crosspoint Switch
• Circuit: 1 x 16:8
• Voltage Supply Source: Dual Supply
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Array Configuration: 16x8
• Number Of Arrays: 1
• Screening Level: Industrial
• Pin Count: 80
• Package Type: LQFP
• Power Supply Requirement: Dual
• Lead Free Status / RoHS Status: Not Compliant

AD8110/AD8111
This will ensure that the programming matrix is always in a
known state. From then on, parallel programming can be used
to modify a single output or more at a time.
In a similar fashion, if both CE and UPDATE are taken LOW
after initial power-up, the random power-up data in the shift
register will be programmed into the matrix. Therefore, in order to
prevent the crosspoint from being programmed into an unknown
state do not apply low logic levels to both CE and UPDATE after
power is initially applied. Programming the full shift register one
time to a desired state by either serial or parallel programming
after initial power-up will eliminate the possibility of program-
ming the matrix to an unknown state.
To change an output’s programming via parallel programming,
SER/PAR and UPDATE should be taken HIGH and CE should
be taken LOW. The CLK signal should be in the HIGH state.
The address of the output that is to be programmed should be
put on A0–A2. The first four data bits (D0–D3) should contain the
information that identifies the input that is programmed to the
output that is addressed. The fourth data bit (D4) will determine
the enabled state of the output. If D4 is LOW (output disabled),
the data on D0–D3 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a HIGH-to-LOW
transition of the CLK signal. The matrix will not be programmed,
however, until the UPDATE signal is taken low. Thus, it is
possible to latch in new data for several or all of the outputs first
via successive negative transitions of CLK while UPDATE is
held high, and then have all the new data take effect when
UPDATE goes LOW. This technique should be used when
programming the device for the first time after power-up when
using parallel programming.
POWER-ON RESET
When powering up the AD8110/AD8111 it is usually desirable
to have the outputs come up in the disabled state. The RESET
pin, when taken LOW will cause all outputs to be in the dis-
abled state. However, the RESET signal does not reset all registers
in the AD8110/AD8111. This is important when operating in
the parallel programming mode. Please refer to that section for
information about programming internal registers after power-
up. Serial programming will program the entire matrix each
time, so no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix or else the matrix can
enter unknown states. To prevent this, do not apply logic low signals
to both CE and UPDATE initially after power-up. The shift register
should first be loaded with the desired data, and then UPDATE
can be taken LOW to program the device.
The RESET pin has a 20 kΩ pull-up resistor to DVDD that can
be used to create a simple power-up reset circuit. A capacitor
from RESET to ground will hold RESET LOW for some time
while the rest of the device stabilizes. The LOW condition will
cause all the outputs to be disabled. The capacitor will then
charge through the pull-up resistor to the HIGH state; thus
allowing full programming capability of the device.
GAIN SELECTION
The 16 × 8 crosspoints come in two versions depending on the
desired gain of the analog circuit paths. The AD8110 device is
unity gain and can be used for analog logic switching and other
applications where unity gain is desired. The AD8110 can also
be used for the input and interior sections of larger crosspoint
arrays where termination of output signals is not usually used.
The AD8110 outputs have a very high impedance when their
outputs are disabled.
For devices that will be used to drive a terminated cable with its
outputs, the AD8111 can be used. This device has a built-in
gain of two that eliminates the need for a gain-of-two buffer to
drive a video line. Because of the presence of the feedback network
in these devices, the disabled output impedance is about 1 kΩ.
If external amplifiers are used to provide a gain = +2, Analog
Devices’ AD8079 provides a fixed G = +2 function.
CREATING LARGER CROSSPOINT ARRAYS
The AD8110/AD8111 are high-density building blocks for
creating crosspoint arrays of dimensions larger than 16 × 8.
Various features such as output disable, chip enable, and gain-
of-one- and-two options are useful for creating larger arrays.
For very large arrays, they can be used along with the AD8116,
a 16 × 16 video crosspoint device. In addition, when required
for customizing a crosspoint array size, they can be used with
the AD8108 and AD8109, a pair (unity gain and gain-of-two)
of 8 × 8 video crosspoint switches.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required.
The 16 × 8 architecture of the AD8110/AD8111 contains 128
“points,” which is a factor of 32 greater than a 4 × 1 crosspoint.
The PC board area and power consumption savings are readily
apparent when compared to using these smaller devices.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the avail-
ability of that input to be a source for any other outputs.
Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than
this minimum. These systems have connectivity available on a
statistical basis that is determined when designing the overall system.