AD8111AST Analog Devices Inc, AD8111AST Datasheet - Page 15

• Manufacturer Part Number: AD8111AST
• Description: IC VIDEO CROSSPOINT SWIT 80LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD8111AST

• Rohs Status: RoHS non-compliant
• Function: Video Crosspoint Switch
• Circuit: 1 x 16:8
• Voltage Supply Source: Dual Supply
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Array Configuration: 16x8
• Number Of Arrays: 1
• Screening Level: Industrial
• Pin Count: 80
• Package Type: LQFP
• Power Supply Requirement: Dual
• Lead Free Status / RoHS Status: Not Compliant

THEORY OF OPERATION
The AD8110 (G = +1) and AD8111 (G = +2) share a common
core architecture consisting of an array of 128 transconductance
(gm) input stages organized as eight 16:1 multiplexers with a
common, 16-line analog input bus. Each multiplexer is basically
a folded-cascode high-speed voltage feedback amplifier with 16
input stages. The input stages are NPN differential pairs whose
differential current outputs are combined at the output stage,
which contains the high impedance node, compensation and a
complementary emitter follower output buffer. In the AD8110,
the output of each multiplexer is fed directly back to the inverting
inputs of its 16 gm stages. In the AD8111, the feedback network
is a voltage divider consisting of two equal resistors.
This switched-gm architecture results in a low power crosspoint
switch that is able to directly drive a back terminated video load
(150 Ω) with low distortion (differential gain and differential
phase errors are better than 0.02% and 0.02°, respectively). This
design also achieves high input resistance and low input capaci-
tance without the signal degradation and power dissipation of
additional input buffers. However, the small input bias current at
any input will increase almost linearly with the number of out-
puts programmed to that input.
The output disable feature of these crosspoints allows larger
switch matrices to be built simply by busing together the outputs
of multiple 16 × 8 ICs. However, while the disabled output imped-
ance of the AD8110 is very high (10 MΩ), that of the AD8111
is limited by the resistive feedback network (which has a nominal
total resistance of 1 kΩ) that appears in parallel with the disabled
output. If the outputs of multiple AD8111s are connected through
separate back termination resistors, the loading due to these
finite output impedances will lower the effective back termination
impedance of the overall matrix. This problem is eliminated if
the outputs of multiple AD8111s are connected directly and
share a single back termination resistor for each output of the
overall matrix. This configuration increases the capacitive loading
of the disabled AD8111 on the output of the enabled AD8111.
APPLICATIONS
The AD8110/AD8111 have two options for changing the
programming of the crosspoint matrix. In the first option, a serial
word of 40 bits can be provided that will update the entire matrix
each time. The second option allows for changing a single
output’s programming via a parallel interface. The serial option
requires fewer signals, but requires more time (clock cycles) for
changing the programming, while the parallel programming tech-
nique requires more signals, but can change a single output at a
time and requires fewer clock cycles to complete programming.
Serial Programming
The serial programming mode uses the device pins CE, CLK,
DATA IN, UPDATE, and SER/PAR. The first step is to assert
a LOW on SER/PAR in order to enable the serial programming
mode. CE for the chip must be LOW to allow data to be clocked
into the device. The CE signal can be used to address an indi-
vidual device when devices are connected in parallel.
The UPDATE signal should be HIGH during the time that data
is shifted into the device’s serial port. Although the data will still
shift in when UPDATE is LOW, the transparent, asynchronous
latches will allow the shifting data to reach the matrix. This will
cause the matrix to try to update to every intermediate state as
defined by the shifting data.
The data at DATA IN is clocked in at every down edge of CLK.
A total of 40 data bits must be shifted in to complete the program-
ming. For each of the eight outputs, there are four bits (D0–D3)
that determine the source of its input followed, by one bit (D4)
that determines the enabled state of the output. If D4 is LOW
(output disabled) the four associated bits (D0–D3) do not matter,
because no input will be switched to that output.
The most significant output address data is shifted in first, then
following in sequence until the least significant output address
data is shifted in. At this point UPDATE can be taken LOW,
which will cause the programming of the device according to the
data that was just shifted in. The UPDATE registers are asyn-
chronous and when UPDATE is LOW (and CE is LOW), they
are transparent.
If more than one AD8110/AD8111 device is to be serially pro-
grammed in a system, the DATA OUT signal from one device
can be connected to the DATA IN of the next device to form a
serial chain. All of the CLK, CE, UPDATE and SER/PAR pins
should be connected in parallel and operated as described above.
The serial data is input to the DATA IN pin of the first device
of the chain, and it will ripple on through to the last. Therefore,
the data for the last device in the chain should come at the begin-
ning of the programming sequence. The length of the programming
sequence will be 40 times the number of devices in the chain.
Parallel Programming
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification
of a single output at a time. Since this takes only one CLK/
UPDATE cycle, significant time savings can be realized by
using parallel programming.
One important consideration in using parallel programming is
that the RESET signal does not reset all registers in the AD8110/
AD8111. When taken low, the RESET signal will only set each
output to the disabled state. This is helpful during power-up to
ensure that two parallel outputs will not be active at the same time.
After initial power-up, the internal registers in the device will
generally have random data, even though the RESET signal
was asserted. If parallel programming is used to program one
output, that output will be properly programmed, but the rest
of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that all outputs be
programmed to a desired state after power-up.
AD8110/AD8111