PI3VDP101LSZDEX Pericom Semiconductor, PI3VDP101LSZDEX Datasheet - Page 9

• Manufacturer Part Number: PI3VDP101LSZDEX
• Manufacturer: Pericom Semiconductor

Specifications of PI3VDP101LSZDEX

• Lead Free Status / Rohs Status: Supplier Unconfirmed

TMDS Outputs
The level shifter's TMDS outputs are required to meet HDMI 1.3 specifi cations.
The HDMI 1.3 Specifi cation is assumed to be the correct reference in instances where this document confl icts
with the HDMI 1.3 specifi cation.
Differential Output Characteristics for TMDS_OUT signals
Symbol
V
V
V
I
T
T
T
T
T
OFF
R
F
SKEW-INTRA
SKEW-INTER
JIT
H
L
SWING
09-0021
Parameter
Single-ended
high level output
voltage
Single-ended
low level output
voltage
Single-ended out-
put swing voltage
Single-ended
current in High-Z
state
Rise time
Fall time
Intra-pair
differential skew
Inter-pair lane-to-
lane output skew
Jitter added to
TMDS signals
Min
AVDD-10mV
AVDD-600mV
450mV
125ps
125ps
Nom
AVDD
AVDD-500mV
500mV
Shifter with Integrated I
9
Max
AVDD+10mV
AVDD-400mV
600mV
10
0.4Tbit
0.4Tbit
30
100
25
Dual Mode DisplayPort™ to HDMI™ Level
Units Comments
V
V
V
μA
ps
ps
ps
ps
ps
2
C ID for HDMI™ Detection
AVDD is the DC termination
voltage in the HDMI or DVI
Sink. AVDD is nominally
3.3V
The open-drain output pulls
down from AVDD.
Swing down from TMDS
termination voltage (3.3V ±
10%)
Measured with TMDS out-
puts pulled up to AVDD Max
(3.6V)through 50Ω resistors.
Max Rise/Fall time
@2.7Gbps = 148ps
125ps = 148-15%
Max Rise/Fall time
@2.7Gbps = 148ps
125ps = 148-15%
This differential skew budget
is in addition to the skew
presented between D+ and
D- paired input pins. HDMI
revision 1.3 source allowable
intra-pair skew is 0.15 Tbit.
This lane-to-lane skew budget
is in addition to skew between
differential input pairs
Jitter budget for TMDS
signals as they pass through
the level shifter. 25ps = 0.056
Tbit at 2.25 Gbps
PS8955B
PI3VDP101LS
11/17/09