PI3VDP101LSZDEX Pericom Semiconductor, PI3VDP101LSZDEX Datasheet - Page 3

• Manufacturer Part Number: PI3VDP101LSZDEX
• Manufacturer: Pericom Semiconductor

Specifications of PI3VDP101LSZDEX

• Lead Free Status / Rohs Status: Supplier Unconfirmed

I
Pericom's PI3VDP101LS supports the mandatory DDC buffer ID access sequence per the
VESA approved DisplayPort™ Interoperability guidelines.
I 2 C Transaction
Start
7-bit Address + command
Read data
Acknowledge (1 bit)
Read data
Read data
Not acknowledge (1 bit)
Stop
2
C ROM Block Read/Write format:
09-0021
Transmitting Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 R/W#
Master
Master
Slave
Master
Slave
Slave
Master
Master
1
0
Data Byte N (N = 1 to 14)
0
Shifter with Integrated I
3
Data byte 15
Data Byte 0
0
Dual Mode DisplayPort™ to HDMI™ Level
0
0
0
2
C ID for HDMI™ Detection
1
PS8955B
Mandatory
Mandatory
Mandatory
Mandatory
Mandatory
Master
−
−
−
PI3VDP101LS
Status
Mandatory
Mandatory
Mandatory
Slave
−
−
−
−
−
11/17/09